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National Semiconductor 54ABT16245W-QML - 54ABT16245W-QML (National Semiconductor) - 16-Bit Transceiver with TRI-STATE Outputs
| Наименование: | 54ABT16245W-QML |
|---|---|
| Производитель: | National Semiconductor |
| Файл: | 54ABT16245W-QML_National Semiconductor.pdf |
| Скачать datasheet: |
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| Описание: | 54ABT16245 16-Bit Transceiver with TRI-STATE Outputs 54ABT16245 August 1998 54ABT16245 16-Bit Transceiver with TRI-STATE В® Outputs General The ’ABT16245 contains sixteen non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. Each byte has separate control inputs which can be shorted together for full 16-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. n Separate control logic for each byte n 16-bit version of the ’ABT245 n A and B output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9317501 Features n Bidirectional non-inverting buffers Military 54ABT16245W-QML Package Number WA48A Package 48-Lead Cerpack Logic Symbol DS100200-1 Pin Pin Names OEn T/Rn A0–A15 B0–B15 Output Enable Input (Active Low) Transmit/Receive Input Side A Inputs/Outputs Side B Inputs/Outputs TRI-STATE В® is a registered trademark of National Semiconductor Corporation. В© 1998 National Semiconductor Corporation DS100200 www.national.com 1 PrintDate=1998/08/27 PrintTime=14:50:42 44961 ds100200 Rev. No. 1 cmserv Proof 1 Connection Diagram Pin Assignment for Cerpack Logic Diagrams DS100200-3 DS100200-2 Functional The ’ABT16245 contains sixteen non-inverting bidirectional buffers with TRI-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. DS100200-4 Truth Table Inputs OE1 L L H Inputs OE2 L L H T/R2 L H X Bus B8–B15 Data to Bus A8–A Bus A8–A15 Data to Bus B8–B 15 15 15 Outputs L H X Bus B0–B7 Data to Bus A0–A Bus A0–A7 Data to Bus B0–B T/R1 7 7 7 HIGH-Z State on A0–A7, B0–B Outputs HIGH-Z State on A8–A15, B8–B H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance www.national.com 2 PrintDate=1998/08/27 PrintTime=14:50:42 44961 ds100200 Rev. No. 1 cmserv Proof 2 Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State в€’65ЛљC to +150ЛљC в€’55ЛљC to +125ЛљC в€’55ЛљC to +175ЛљC в€’0.5V to +7.0V в€’0.5V to +7.0V в€’30 mA to +5.0 mA Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) twice the rated IOL (mA) в€’500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input в€’55ЛљC to +125ЛљC +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns в€’0.5V to 5.5V в€’0.5V to VCC Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IBVIT IIL VID IIH + I OZH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown Test (I/O) Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Outputs Enabled Outputs TRI-STATE Outputs TRI-STATE 54ABT 54ABT 54ABT ABT16245 Min Typ Max 2.0 0.8 в€’1.2 2.5 2.0 0.55 5 5 7 100 в€’5 в€’5 4.75 50 в€’50 в€’100 в€’275 50 100 100 60 100 2.5 2.5 50 Units V V V V V V ВµA ВµA ВµA ВµA V ВµA ВµA mA ВµA ВµA ВµA mA ВµA mA mA ВµA VCC Conditions Recognized HIGH Signal Recognized LOW Signal Min Min Min Min Max Max Max Max 0.0 0в€’ 5.5V 0в€’ 5.5V Max Max 0.0 Max Max Max IIN = в€’18 mA (OEn, T/Rn) IOH = в€’3 mA (An, Bn) IOH = в€’24 mA (An, Bn) IOL = 48 mA (An, Bn) VIN = 2.7V (OEn, T/Rn) (Note 3) VIN = VCC (OEn, T/Rn) VIN = 7.0V (OEn, T/Rn) VIN = 5.5V (An, Bn) VIN = 0.5V (OEn, T/Rn) (Note 3) VIN = 0.0V (OEn, T/Rn) IID = 1.9 ВµA (OEn, T/Rn) All Other Pins Grounded VOUT = 2.7V (An, Bn); OE = 2.0V VOUT = 0.5V (An, Bn); OE = 2.0V VOUT = 0.0V (An, Bn) VOUT = V CC IIL + I OZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT (An, Bn) VOUT = 5.50V (An, Bn); All Others GND All Outputs HIGH All Outputs LOW OEn = VCC, T/Rn = GND or VCC All others at VCC or GND VI = V CC в€’ 2.1V Max OEn, T/ Rn VI = VCC в€’ 2.1V Data Input VI = VCC в€’ 2.1V All others at VCC or GND 3 www.national.com PrintDate=1998/08/27 PrintTime=14:50:43 44961 ds100200 Rev. No. 1 cmserv Proof 3 DC Electrical Characteristics Symbol ICCD Dynamic ICC Parameter No Load (Continued) ABT16245 Min Typ Max mA/ 0.1 MHz Max Outputs Open OEn = GND, T/Rn = GND or VCC One Bit Toggling, 50% Duty Cycle Units VCC Conditions Note 3: Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 54ABT TA = в€’55ЛљC to +125ЛљC VCC = 4.5V–5.5V CL = 50 pF Min tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation Delay Data to Outputs Output Enable Time Output Disable Time 0.8 0.9 1.3 1.0 6.4 6.9 6.9 6.9 ns ns 0.5 0.5 Max 4.5 5.2 ns Units Fig. No. Figure 5 Figure 4 Figure 4 Capacitance Symbol CIN CI/O (Note 4) Parameter Input Capacitance Output Capacitance Typ 5 11 Units pF pF Conditions, TA = 25ЛљC VCC = 0.0V (OEn, T/Rn) VCC = 5.0V (An, Bn) Note 4: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. tPLH vs Temperature (TA) CL = 50 pF, 1 Output Switching tPHL vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100200-13 DS100200-14 www.national.com 4 PrintDate=1998/08/27 PrintTime=14:50:43 44961 ds100200 Rev. No. 1 cmserv Proof 4 Capacitance (Continued) tPHL vs Load Capacitance 1 Output Switching, TA = 25ЛљC tPLH vs Load Capacitance 1 Output Switching, TA = 25ЛљC DS100200-15 DS100200-16 tPLH vs Load Capacitance 16 Outputs Switching, TA = 25ЛљC tPHL vs Load Capacitance 16 Outputs Switching, TA = 25ЛљC DS100200-17 DS100200-18 tPZL vs Temperature (TA) CL = 50 pF, 1 Output Switching tPLZ vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100200-19 DS100200-20 tPZH vs Temperature (TA) CL = 50 pF, 1 Output Switching tPHZ vs Temperature (TA) CL = 50 pF, 1 Output Switching DS100200-21 DS100200-22 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Table. 5 www.national.com PrintDate=1998/08/27 PrintTime=14:50:43 44961 ds100200 Rev. No. 1 cmserv Proof 5 Capacitance (Continued) tPHZ vs Temperature (TA) CL = 50 pF, 16 Outputs Switching tPZH vs Temperature (TA) CL = 50 pF, 16 Outputs Switching DS100200-23 DS100200-24 tPZL vs Temperature (TA) CL = 50 pF, 16 Outputs Switching tPLZ vs Temperature (TA) CL = 50 pF, 16 Outputs Switching DS100200-26 DS100200-25 tPZL vs Load Capacitance 16 Outputs Switching TA = 25ЛљC tPZH vs Load Capacitance 16 Outputs Switching TA = 25ЛљC DS100200-27 DS100200-28 tPLH vs Number Output Switching VCC = 5.0V, TA = 25ЛљC, CL = 50 pF tPHL vs Number Output Switching VCC = 5.0V, TA = 25ЛљC, CL = 50 pF DS100200-29 DS100200-30 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Table. www.national.com 6 PrintDate=1998/08/27 PrintTime=14:50:43 44961 ds100200 Rev. No. 1 cmserv Proof 6 Capacitance (Continued) ICC vs Frequency Average, TA = 25ЛљC, VCC = 5.5V All Outputs Unloaded/Unterminated; 16 Outputs Switching In-Phase at 50 Duty Cycle DS100200-31 Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Table. 7 www.national.com PrintDate=1998/08/27 PrintTime=14:50:43 44961 ds100200 Rev. No. 1 cmserv Proof 7 AC Loading DS100200-9 DS100200-5 *Includes jig and probe capacitance FIGURE 5. Propagation Delay Waveforms for Inverting and Non-Inverting Functions Book Extract End FIGURE 1. Standard AC Test Load DS100200-7 FIGURE 2. Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tw 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements DS100200-8 FIGURE 4. TRI-STATE Output HIGH and LOW Enable and Disable Times www.national.com 8 PrintDate=1998/08/27 PrintTime=14:50:44 44961 ds100200 Rev. No. 1 cmserv Proof 8 THIS PAGE IS IGNORED IN THE DATABOOK 9 9 PrintDate=1998/08/27 PrintTime=14:50:44 44961 ds100200 Rev. No. 1 cmserv Proof 9 54ABT16245 16-Bit Transceiver with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Cerpack NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected |
