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Texas Instruments 54ACT11030 - 54ACT11030 (Texas Instruments) - 8-INPUT POSITIVE-NAND GATES
| Наименование: | 54ACT11030 |
|---|---|
| Производитель: | Texas Instruments |
| Файл: | 54ACT11030_Texas Instruments.pdf |
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| Описание: | 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC в„ў (Enhanced-Performance Implanted CMOS) 1-Вµm Process 500-mA Typical Latch-Up Immunity at 125В°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 54ACT11030 . . . J PACKAGE 74ACT11030 . . . D OR N PACKAGE (TOP VIEW) C B A GND Y NC NC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 D E F VCC NC G H 54ACT11030 . . . FK PACKAGE (TOP VIEW) description These devices contain a single 8-input NAND gate and perform the following Boolean functions in positive logic: Y = A • B • C • D • E • F • G • H or Y=A+B+C+D+E+F+G+H The 54ACT11030 is characterized for operation over the full military temperature range of – 55В°C to 125В°C. The 74ACT11030 is characterized for operation from – 40В°C to 85В°C. FUNCTION TABLE INPUTS A THRU H All inputs H One or more inputs L OUTPUT Y L H D NC C NC B 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 E F NC V CC NC G NC H NC NC NC – No internal connection logic symbol†A B C D E F G H 3 2 1 14 13 12 9 8 5 Y & logic diagram (positive logic) A B C D E F G H 3 2 1 14 13 12 9 8 5 Y †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A GND NC Y NC Copyright В© 1993, Texas Instruments Incorporated 2–1 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65В°C to 150В°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions 54ACT11030 MIN VCC VIH VIL VI VO IOH IOL ∆t /∆v TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 – 55 0 0 4.5 2 0.8 VCC VCC – 24 24 10 125 0 – 40 0 0 MAX 5.5 74ACT11030 MIN 4.5 2 0.8 VCC VCC – 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/ V В°C 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 ВµA VOH IOH = – 24 mA IOH = – 50 mA†IOH = – 75 mA†IOL = 50 ВµA VOL IOL = 24 mA IOL = 50 mA†IOL = 75 mA†II ICC ∆ICC‡ VI = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V В± 0.1 4 0.9 В±1 80 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 В±1 40 1 ВµA ВµA mA pF MIN 4.4 5.4 3.94 4.94 TA = 25В°C TYP MAX 54ACT11030 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT11030 MIN 4.4 5.4 3.8 4.8 V MAX UNIT One input at 3.4 V, Other inputs at VCC or GND Ci VI = VCC or GND 5V 3.5 †Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. switching characteristics over recommended operating free-air temperature range, VCC = 5 V В± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) A thru H TO (OUTPUT) Y MIN 1.5 1.5 TA = 25В°C TYP MAX 5.4 5.9 8.1 7.8 54ACT11030 MIN 1.5 1.5 MAX 8.8 9.3 74ACT11030 MIN 1.5 1.5 MAX 8.5 8.7 UNIT ns operating characteristics, VCC = 5 V, TA = 25В°C PARAMETER Cpd Power dissipation capacitance per gate TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 41 UNIT pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 54ACT11030, 74ACT11030 8-INPUT POSITIVE-NAND GATES SCLS050 – MARCH 1987 – REVISED APRIL 1993 PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) 500 Ω Output Input (see Note B) tPHL 3V 1.5 V 1.5 V 0V tPLH VOH 50% VCC VOL LOAD CIRCUIT VOLTAGE WAVEFORMS 50% VCC NOTES: A. CL includes probe and jig capacitance. B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright В© 1998, Texas Instruments Incorporated |
