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Texas Instruments 54ACT11109 - 54ACT11109 (Texas Instruments) - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
| Наименование: | 54ACT11109 |
|---|---|
| Производитель: | Texas Instruments |
| Файл: | 54ACT11109_Texas Instruments.pdf |
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| Описание: | 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC в„ў (Enhanced-Performance Implanted CMOS) 1-Вµm Process 500-mA Typical Latch-Up Immunity at 125В°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs 54ACT11109 . . . J PACKAGE 74ACT11109 . . . D OR N PACKAGE (TOP VIEW) 1PRE 1Q 1Q GND 2Q 2Q 2PRE 2CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 1CLK 1K 1J 1CLR VCC 2CLR 2J 2K description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (1PRE or 2PRE) or clear (1CLR or 2CLR) input sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. 54ACT11109 . . . FK PACKAGE (TOP VIEW) 1J 1CLR NC VCC 1K 1CLK NC 1PRE 1Q 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 2CLR 2J 2K NC 2CLK 2PRE 1Q GND NC OUTPUTS J X X X L H L H X K X X X L L H H X H Q0 Q H L H†L Toggle Q0 Q0 L Q L H H†H NC – No internal connection The 54ACT11109 is characterized for operation over the full military temperature range of – 55В°C to 125В°C. The 74ACT11109 is characterized for operation from – 40В°C to 85В°C. FUNCTION TABLE INPUTS PRE L H L H H H H H CLR H L L H H H H H CLK X X X ↑ ↑ ↑ ↑ L Q0 †This configuration is nonstable; that is, it will not persist when either PRE or CLR returns to the inactive (high) level. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright В© 1993, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Q 2Q 2–1 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 logic symbol†1 1PRE 1J 1CLK 1K 1CLR 2PRE 2J 2CLK 2K 11 2CLR †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 14 16 15 13 7 10 8 9 5 2Q 6 2Q S 1J C1 1K R 3 1Q 2 1Q absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В± 100 mA Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65В°C to 150В°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. recommended operating conditions 54ACT11109 MIN VCC VIH VIL VI VO IOH IOL ∆t /∆v TA Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature 0 – 55 0 0 4.5 2 0.8 VCC VCC – 24 24 10 125 0 – 40 0 0 MAX 5.5 74ACT11109 MIN 4.5 2 0.8 VCC VCC – 24 24 10 85 MAX 5.5 UNIT V V V V V mA mA ns/ V В°C 2–2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = – 50 ВµA VOH IOH = – 24 mA IOH = – 50 mA†IOH = – 75 mA†IOL = 50 ВµA VOL IOL = 24 mA IOL = 50 mA†IOL = 75 mA†II ICC ∆ICC‡ VI = VCC or GND VI = VCC or GND, IO = 0 VCC 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 4.5 V 5.5 V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V В± 0.1 4 0.9 В±1 80 1 0.1 0.1 0.36 0.36 0.1 0.1 0.5 0.5 1.65 1.65 В±1 40 1 ВµA ВµA mA pF MIN 4.4 5.4 3.94 4.94 TA = 25В°C TYP MAX 54ACT11109 MIN 4.4 5.4 3.7 4.7 3.85 3.85 0.1 0.1 0.44 0.44 V MAX 74ACT11109 MIN 4.4 5.4 3.8 4.8 V MAX UNIT One input at 3.4 V, Other inputs at VCC or GND Ci VI = VCC or GND 5V 3.5 †Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. timing requirements over recommended operating free-air temperature range, VCC = 5 V В± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25В°C MIN MAX fclock tw tsu th Clock frequency Pulse duration Setup time before CLK↑ Hold time, data after CLK↑ PRE or CLR low CLK high or low Data high or low PRE or CLR inactive 0 5.5 5 5.5 2 0 100 54ACT11109 MIN 0 5.5 5 5.5 2 0 MAX 100 74ACT11109 MIN 0 5.5 5 5.5 2 0 MAX 100 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V В± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) MIN 100 PRE or CLR CLK 1.5 Q or Q Q or Q 1.5 1.5 1.5 TA = 25В°C TYP MAX 125 5.5 6 6 5.5 8.6 10.8 8.3 7.6 54ACT11109 MIN 100 1.5 1.5 1.5 1.5 9.8 12.6 9.7 9 MAX 74ACT11109 MIN 100 1.5 1.5 1.5 1.5 9.2 11.8 9.1 8.3 MAX UNIT MHz ns ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2–3 54ACT11109, 74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993 operating characteristics, VCC = 5 V, TA = 25В°C PARAMETER Cpd Power dissipation capacitance per flip-flop TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 31 UNIT pF PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 50 pF (see Note A) 500 Ω tw 3V Input 1.5 V 1.5 V 0V LOAD CIRCUIT VOLTAGE WAVEFORMS Input (see Note B) Timing Input (see Note B) tsu Data Input 1.5 V 3V 1.5 V 0V th 3V 1.5 V 0V Out-of-Phase Output VOLTAGE WAVEFORMS tPHL In-Phase Output tPLH 3V 1.5 V 1.5 V 0V tPHL 50% VCC VOH 50% VCC VOL tPLH 50% VCC VOH 50% VCC VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 2–4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize |
