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Texas Instruments 74221 - 74221 (Texas Instruments) - High Speed CMOS Logic Dual Monostable Multivibrator with Reset

Наименование: 74221
Производитель: Texas Instruments
Файл: 74221_Texas Instruments.pdf
Скачать datasheet: Texas Instruments 74221 - 74221 (Texas Instruments) - High Speed CMOS Logic Dual Monostable Multivibrator with Reset
Описание: Data sheet acquired from Harris Semiconductor SCHS166A CD74HC221, CD74HCT221 High Speed CMOS Logic Dual Monostable Multivibrator with Reset The CD74HC221, and CH74HCT221 are dual monostable multivibrators with reset. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing Edge triggering (A) and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, RX, is typically 500Ω. The minimum value of external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.7 RXCX at VCC = 4.5V. November 1997 - Revised April 1999 Features • Overriding RESET Terminates Output Pulse • Triggering from the Leading or Trailing Edge • Q and Q Buffered Outputs • Separate Resets • Wide Range of Output-Pulse Widths • Schmitt Trigger on B Inputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide Operating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Signiп¬Ѓcant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1ВµA at VOL, VOH [ /Title (CD74 HC221 , CD74 HCT22 1) /Subject (High Speed CMOS Logic Dual Monos table Multi- Ordering Information PART NUMBER CD74HC221E CD74HCT221E CD74HC221M CD74HCT221M NOTES: 1. When ordering, use the entire part number. Add the sufп¬Ѓx 96 to obtain the variant in the tape and reel. 2. Wafer or die are available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information. TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 16 Ld PDIP 16 Ld PDIP 16 Ld SOIC 16 Ld SOIC PKG. NO. E16.3 E16.3 M16.15 M16.15 Pinout CD74HC221, CD74HCT221 (PDIP, SOIC) TOP VIEW 1A 1 1B 2 1R 3 1Q 4 2Q 5 2CX 6 2CXRX 7 GND 8 16 VCC 15 1CXRX 14 1CX 13 1Q 12 2Q 11 2R 10 2B 9 2A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright В© Harris Corporation 1997 File Number 1670.1 1 CD74HC221, CD74HCT221 Functional Diagram 1CX 14 1CX 1A 1 1B 2 1R 3 11 9 2A 10 2B 2CX 6 2CX 2CXRX 7 VCC 2RX MONO 2 12 2Q 5 2Q MONO 1 4 1Q 1RX VCC 15 1CXRX 13 1Q 2R TRUTH TABLE INPUTS A H X L ↓ X L B X L ↑ H X H R H H H H L ↑ (Note 3) (Note 3) L H Q L L OUTPUTS Q H H NOTE: H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low Level, = One High Level Pulse, = One Low Level Pulse 3. For this combination the reset input must be low and the following sequence must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1 (or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from low-to-high and the device will be triggered. 2 CD74HC221, CD74HCT221 Logic Diagram VCC C 16 P RX N A 1 (9) 2 (10) B 3 (11) P VCC R D RESET FF S R Q VCC MIRROR VOLTAGE QM QM MASK FF R S MAIN FF Q N PULLDOWN FF D C 4 (12) Q (13) 5 Q C R Q Q N 8 R1 R4 PP R3 C C P OP AMP R2 + R 15 (7) RXCX CX Q 14 (6) CX GND VCC + OP AMP 3 CD74HC221, CD74HCT221 Absolute Maximum Ratings DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .В±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .В±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .В±25mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .В±25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .В±50mA Thermal Information Thermal Resistance (Typical, Note 4) ОёJA (oC/W) ОёJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 100 N/A SOIC Package . . . . . . . . . . . . . . . . . . . 180 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time, tr, tf on Inputs A and R 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max) Input Rise and Fall Time, tr, tf on Input B 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited ns (Max) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciп¬Ѓcation is not implied. NOTE: 4. ОёJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Speciп¬Ѓcations TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -4 -5.2 0.02 0.02 0.02 4 5.2 2 4.5 6 4.5 6 2 4.5 6 4.5 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 V V V V V V V V V V V V V V V V V V SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS 4 CD74HC221, CD74HCT221 DC Electrical Speciп¬Ѓcations (Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC ∆ICC VCC and GND VCC or GND VCC -2.1 VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL II ICC VI (V) VCC or GND VCC or GND IO (mA) 0 VCC (V) 6 6 25oC MIN TYP MAX В±0.1 8 -40oC TO 85oC -55oC TO 125oC MIN MAX В±1 80 MIN MAX В±1 160 UNITS ВµA ВµA -4 4.5 3.98 - - 3.84 - 3.7 - V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 4 4.5 - - 0.26 - 0.33 - 0.4 V 0 0 - 5.5 5.5 4.5 to 5.5 100 В±0.1 8 360 - В±1 80 450 - В±1 160 490 ВµA ВµA ВµA NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) speciп¬Ѓcation is 1.8mA. HCT Input Loading Table INPUT All Inputs UNIT LOADS 0.3 NOTE: Unit Load is ∆ICC limit speciп¬Ѓed in DC Electrical Table, e.g., 360ВµA max at 25oC. Prerequisite For Switching Function 25oC PARAMETER HC TYPES Input Pulse Width A tWL 2 4.5 6 Input Pulse Width B tWH 2 4.5 6 70 14 12 70 14 12 90 18 15 90 18 15 105 21 18 105 21 18 ns ns ns ns ns ns SYMBOL VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS 5 CD74HC221, CD74HCT221 Prerequisite For Switching Function (Continued) 25oC PARAMETER Input Pulse Width Reset SYMBOL tWL VCC (V) 2 4.5 6 Recovery Time R to A or B tSU 2 4.5 6 Output Pulse Width Q or Q CX = 0.1ВµF RX = 10kΩ Output Pulse Width Q or Q CX = 28pF, RX = 2kΩ CX = 1000pF, RX = 2kΩ CX = 1000pF, RX = 10kΩ HCT TYPES Input Pulse Width A Input Pulse Width B Input Pulse Width Reset Recovery Time R to A or B Output Pulse Width Q or Q CX = 0.1ВµF RX = 10kΩ Output Pulse Width Q or Q CX = 28pF, RX = 2kΩ CX = 1000pF, RX = 2kΩ CX = 1000pF, RX = 10kΩ tWL tWH tWL tSU tW tW tW tW 4.5 4.5 4.5 4.5 5 4.5 4.5 4.5 14 14 18 0 630 140 1.5 7 770 18 18 23 0 602 798 21 21 27 0 595 805 ns ns ns ns Вµs ns Вµs Вµs tW tW tW tW 5 4.5 4.5 4.5 MIN 70 14 12 0 0 0 630 TYP 140 1.5 7 MAX 770 -40oC TO 85oC MIN 90 18 15 0 0 0 602 MAX 798 -55oC TO 125oC MIN 105 21 18 0 0 0 595 MAX 805 UNITS ns ns ns ns ns ns Вµs ns Вµs Вµs Switching Speciп¬Ѓcations Input tr, tf = 6ns TEST CONDITIONS 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS PARAMETER HC TYPES Propagation Delay, Trigger A, B, R to Q SYMBOL tPLH CL = 50pF CL = 50pF CL = 50pF CL = 15pF 2 4.5 6 5 2 4.5 6 5 - 18 14 210


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