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Fairchild Semiconductor 74AC109MTC - 74AC109MTC (Fairchild Semiconductor) - Dual JK Positive Edge-Triggered Flip-Flop
| Наименование: | 74AC109MTC |
|---|---|
| Производитель: | Fairchild Semiconductor |
| Файл: | 74AC109MTC_Fairchild Semiconductor.pdf |
| Скачать datasheet: |
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| Описание: | 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop March 2007 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Features в– ICC reduced by 50% в– Outputs source/sink 24mA в– ACT109 has TTL-compatible inputs tm General The AC/ACT109 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D-Type flip-flop (refer to AC/ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: – – – – LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Information Order Number 74AC109SC 74AC109SJ 74AC109MTC 74ACT109SC 74AC109MTC 74ACT109PC Package Number M16A M16D MTC16 M16A MTC16 N16E Package 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagram Pin s Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs FACTв„ў is a trademark of Fairchild Semiconductor Corporation. В©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Logic Symbols IEEE/IEC Truth Table Each half. Inputs SD L H L H H H H H Outputs J X X X L H L H CD H L L H H H H H CP X X X K X X X L L H H X Q H L H L Toggle Q0 H Q0 Q L H H H Q0 L Q0 L X H = HIGH Voltage Level L = LOW Voltage Level = LOW-to-HIGH Transition X = Immaterial Q0(Q0) = Previous Q0(Q0) before LOW-to-HIGH Transition of Clock Logic Diagram One half shown. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. В©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 2 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC IIK Supply Voltage DC Input Diode Current VI = –0.5V VI = VCC + 0.5V VI IOK DC Input Voltage DC Output Diode Current VO = –0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage Parameter Rating –0.5V to +7.0V –20mA +20mA –0.5V to VCC + 0.5V –20mA +20mA –0.5V to VCC + 0.5V В±50mA В±50mA –65В°C to +150В°C 140В°C DC Output Source or Sink Current Storage Temperature Junction Temperature ICC or IGND DC VCC or Ground Current per Output Pin Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC Supply Voltage AC ACT VI VO TA ∆V / ∆t ∆V / ∆t Input Voltage Output Voltage Operating Temperature Parameter Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC –40В°C to +85В°C 125mV/ns 125mV/ns Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V В©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 3 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop DC Electrical Characteristics for AC Symbol VIH Parameter Minimum HIGH Level Input Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 TA = +25В°C Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50ВµA TA = –40В°C to +85В°C Guaranteed Limits Units V 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.46 3.76 4.76 0.1 0.1 0.1 0.44 0.44 0.44 В±1.0 75 –75 ВµA mA mA ВµA V V V Typ. 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VIN = VIL or VIH: 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 VIN = VIL or VIH: 3.0 4.5 5.5 IIN(3) IOLD IOHD ICC (3) IOH = –12mA IOH = –24mA IOH = –24mA(1) 0.002 0.001 0.001 IOL = 12mA IOL = 24mA IOL = 24mA(1) VI = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND IOUT = 50ВµA 0.1 0.1 0.1 0.36 0.36 0.36 В±0.1 Maximum Input Leakage Current Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current 5.5 5.5 5.5 2.0 20.0 Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. В©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 4 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop DC Electrical Characteristics for ACT Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 TA = +25В°C Conditions VOUT = 0.1V or VCC – 0.1V VOUT = 0.1V or VCC – 0.1V IOUT = –50ВµA VIN = VIL or VIH: TA = –40В°C to +85В°C Units V V V 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 В± 1.0 1.5 75 –75 ВµA mA mA mA ВµA V Typ. 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 Guaranteed Limits 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 IOH = –24mA IOH = –24mA(4) 0.001 0.001 VIN = VIL or VIH: IOL = 24mA IOL = 24mA(4) VI = VCC, GND VI = VCC – 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 0.6 IOUT = 50ВµA 3.86 4.86 0.1 0.1 0.36 0.36 В±0.1 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(5) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 2.0 20.0 Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time. В©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 5 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop AC Electrical Characteristics for AC TA = +25В°C, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL TA = –40В°C to +85В°C, CL = 50pF Min. 100 125 Parameter Maximum Clock Frequency Propagation Delay, CPn to Qn or Qn Propagation Delay, CPn to Qn or Qn Propagation Delay, CDn or SDn to Qn or Qn Propagation Delay, CDn or SDn to Qn or Qn VCC (V)(6) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Min. 125 150 4.0 2.5 3.0 2.0 3.0 2.5 3.0 2.0 Typ. 150 175 8.0 6.0 8.0 6.0 8.0 6.0 10.0 7.5 Max. Max. Units MHz 13.5 10.0 14.0 10.0 12.0 9.0 12.0 9.5 3.5 2.0 3.0 1.5 2.5 2.0 3.0 2.0 16.0 10.5 14.5 10.5 13.0 10.0 13.5 10.5 ns ns ns ns Note: 6. Voltage range 3.3 is 3.3V В± 0.3V. Voltage range 5.0 is 5.0V В± 0.5V. AC Operating Requirements for AC TA = +25В°C, CL = 50pF Symbol tS tH tW tREC TA = –40В°C to +85В°C, CL = 50 pF Units ns ns ns ns 7.5 5.0 0 0.5 7.5 5.0 0 0 Parameter Setup Time, HIGH or LOW, Jn or Kn to CPn Hold Time, HIGH or LOW, Jn or Kn to CPn Pulse Width, CDn or SDn Recovery Time, CDn or SDn to CPn VCC (V)(7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 Typ. 3.5 2.0 –1.5 –0.5 2.0 2.0 –2.5 –1.5 Guaranteed Minimum 6.5 4.5 0 0.5 7.0 4.5 0 0 Note: 7. Voltage range 3.3 is 3.3V В± 0.3V. Voltage range 5.0 is 5.0V В± 0.5V В©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 6 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop AC Electrical Characteristics for ACT TA = +25В°C, CL = 50pF Symbol fMAX tPLH tPHL tPLH tPHL TA = –40В°C to +85В°C, CL = 50pF Min. 125 3.5 2.5 2.0 2.0 Parameter Maximum Clock Frequency Propagation Delay, CPn to Qn or Qn Propagation Delay, CPn to Qn or Qn Propagation Delay, CDn or SDn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn VCC (V)(8) 5.0 5.0 5.0 5.0 5.0 Min. 145 4.0 3.0 2.5 2.5 Typ. Max. 210 7.0 6.0 5.5 6.0 11.0 10.0 9.5 10.0 Max. 13.0 11.5 10.5 11.5 Units MHz ns ns ns ns Note: 8. Voltage range 5.0 is 5.0V В± 0.5V AC Operating Requirements for ACT TA = +25В°C, CL = 50pF Symbol tS tH tW trec TA = –40В°C to +85В°C, CL = 50pF Units ns ns ns ns 2.5 2.0 6.0 0 Parameter Setup Time, HIGH or LOW, Jn or Kn to CPn Hold Time, HIGH or LOW, Jn or Kn to CPn Pulse Width, CPn or CDn or SDn Recovery Time, CDn or SDn to CPn VCC (V)(9) 5.0 5.0 5.0 5.0 Typ. 0.5 0 3.0 –2.5 Guaranteed Minimum 2.0 2.0 5.0 0 Note: 9. Voltage range 5.0 is 5.0V В± 0.5V Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Conditions VCC = OPEN VCC = 5.0V Typ. 4.5 35.0 Units pF pF В©1988 Fairchild Semiconductor Corporation 74AC109, 74ACT109 Rev. 1.5 www.fairchildsemi.com 7 74AC109, 74ACT109 Dual JK Positive Edge-Triggered Flip-Flop Physical Dimensions Dimensions are in millimeters unless otherwise noted. Figure 1. 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A В©1988 Fairchild Semiconductor Corporation 74AC10 |
