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Philips Semiconductors 74AHC00 - 74AHC00 (Philips Semiconductors) - Quad 2-input NAND gate
| Наименование: | 74AHC00 |
|---|---|
| Производитель: | Philips Semiconductors |
| Файл: | 74AHC00_Philips Semiconductors.pdf |
| Скачать datasheet: |
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| Описание: | INTEGRATED CIRCUITS DATA SHEET 74AHC00; 74AHCT00 Quad 2-input NAND gate Product speciп¬Ѓcation Supersedes data of 1998 Dec 09 File under Integrated Circuits, IC06 1999 Sep 23 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate FEATURES • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V • Balanced propagation delays • All inputs have Schmitt-trigger actions • Inputs accept voltages higher than VCC • For AHC only: operates with CMOS input levels • For AHCT only: operates with TTL input levels • Specified from в€’40 to +85 and +125 В°C. DESCRIPTION The 74AHC/AHCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT00 provides the 2-input NAND function. CI CO CPD Note 1. H = HIGH voltage level; L = LOW voltage level. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 В°C; tr = tf ≤ 3.0 ns. FUNCTION TABLE See note 1. INPUT nA L L H H nB L H L H 74AHC00; 74AHCT00 OUTPUT nY H H H L TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay nA, nB to nY input capacitance output capacitance power dissipation capacitance CL = 50 pF; f = 1 MHz; notes 1 and 2 CONDITIONS AHC CL = 15 pF; VCC = 5 V 3.2 AHCT 3.3 3.0 4.0 7.0 ns pF pF pF UNIT VI = VCC or GND 3.0 4.0 7.0 Notes 1. CPD is used to determine the dynamic power dissipation (PD in ВµW). PD = CPD Г— VCC2 Г— fi + ∑ (CL Г— VCC2 Г— fo) where: fi = input frequency in MHz; fo = output frequency in MHz; ∑ (CL Г— VCC2 Г— fo) = sum of outputs; CL = output load capacitance in pF; VCC = supply voltage in Volts. 2. The condition is VI = GND to VCC. PINNING PIN 1, 4, 9 and 12 2, 5, 10 and 13 3, 6, 8 and 11 7 14 SYMBOL 1A to 4A 1B to 4B 1Y to 4Y GND VCC DESCRIPTION data inputs data inputs data outputs ground (0 V) DC supply voltage 1999 Sep 23 2 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate ORDERING INFORMATION OUTSIDE NORTH AMERICA 74AHC00D 74AHC00PW 74AHCT00D 74AHCT00PW 74AHC00; 74AHCT00 PACKAGES NORTH AMERICA PINS 74AHC00D 74AHC00PW DH 74AHCT00D 74AHCT00PW DH 14 14 14 14 PACKAGE SO TSSOP SO TSSOP MATERIAL plastic plastic plastic plastic CODE SOT108-1 SOT402-1 SOT108-1 SOT402-1 handbook, halfpage 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 MNA210 14 VCC 13 4B handbook, halfpage 12 4A A Y B MNA211 00 11 4Y 10 3B 9 8 3A 3Y Fig.1 Pin configuration. Fig.2 Logic diagram (one gate). handbook, halfpage handbook, halfpage 1 2 & 3 1 2 4 5 9 10 12 13 1A 1B 2A 2B 3A 3B 4A 4B 1Y 3 4 & 6 2Y 6 5 3Y 8 9 10 & 8 4Y 11 12 & 11 MNA212 13 MNA246 Fig.3 Functional diagram. Fig.4 IEC logic symbol. 1999 Sep 23 3 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate RECOMMENDED OPERATING CONDITIONS 74AHC SYMBOL VCC VI VO Tamb PARAMETER DC supply voltage input voltage output voltage operating ambient temperature range see DC and AC characteristics per device VCC = 5 V В±0.5 V CONDITIONS MIN. 2.0 0 0 в€’40 в€’40 74AHC00; 74AHCT00 74AHCT UNIT TYP. MAX. 5.0 в€’ в€’ +25 +25 в€’ в€’ 5.5 5.5 VCC +85 V V V В°C TYP. MAX. MIN. 5.0 в€’ в€’ +25 +25 в€’ в€’ 5.5 5.5 VCC +85 4.5 0 0 в€’40 +125 в€’40 100 20 в€’ в€’ +125 В°C в€’ 20 ns/V tr,tf (∆t/∆f) input rise and fall rates VCC = 3.3 V В±0.3 V в€’ в€’ LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC VI IIK IOK IO ICC Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO packages: above 70 В°C the value of PD derates linearly with 8 mW/K. For TSSOP packages: above 60 В°C the value of PD derates linearly with 5.5 mW/K. PARAMETER DC supply voltage input voltage range DC input diode current DC output diode current DC VCC or GND current storage temperature range power dissipation per package for temperature range: в€’40 to +125 В°C; note 2 VI < в€’0.5 V; note 1 VO < в€’0.5 V or VO > VCC + 0.5 V; note 1 CONDITIONS MIN. MAX. UNIT в€’0.5 в€’0.5 в€’ в€’ в€’ в€’ в€’65 в€’ +7.0 +7.0 в€’20 В±20 В±25 В±75 500 V V mA mA mA mA mW DC output source or sink current в€’0.5 V < VO < VCC + 0.5 V +150 В°C 1999 Sep 23 4 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate DC CHARACTERISTICS 74AHC00; 74AHCT00 74AHC family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH HIGH-level input voltage VCC (V) 2.0 3.0 5.5 VIL LOW-level input voltage 2.0 3.0 5.5 VOH HIGH-level output voltage; all outputs HIGH-level output voltage VI = VIH or VIL; IO = в€’50 ВµA VI = VIH or VIL; IO = в€’4.0 mA VI = VIH or VIL; IO = в€’8.0 mA VOL LOW-level output voltage; all outputs LOW-level output voltage VI = VIH or VIL; IO = 50 ВµA VI = VIH or VIL; IO = 4 mA VI = VIH or VIL; IO = 8 mA II IOZ ICC CI input leakage current 3-state output OFF current quiescent supply current input capacitance VI = VCC or GND 2.0 3.0 4.5 3.0 4.5 2.0 3.0 4.5 3.0 4.5 5.5 MIN. 1.5 2.1 в€’ в€’ в€’ 1.9 2.9 4.4 в€’ в€’ в€’ в€’ в€’ 2.0 3.0 4.5 25 TYP. в€’ в€’ в€’ 0.5 0.9 1.65 в€’ в€’ в€’ в€’ в€’ 0.1 0.1 0.1 0.36 0.36 0.1 Tamb (В°C) в€’40 to +85 в€’ в€’ 0.5 0.9 1.65 в€’ в€’ в€’ в€’40 to +125 UNIT в€’ в€’ 0.5 0.9 1.65 в€’ в€’ в€’ V V V MAX. MIN. MAX. MIN. MAX. 1.5 2.1 в€’ в€’ в€’ 1.9 2.9 4.4 1.5 2.1 в€’ в€’ в€’ 1.9 2.9 4.4 V 3.85 в€’ 3.85 в€’ 3.85 в€’ 2.58 в€’ 3.94 в€’ в€’ в€’ в€’ в€’ в€’ в€’ в€’ в€’ в€’ 0 0 0 в€’ в€’ в€’ в€’ в€’ 3 2.48 в€’ 3.8 в€’ в€’ в€’ в€’ в€’ в€’ в€’ 0.1 0.1 0.1 0.44 0.44 1.0 В±2.5 20 10 2.40 в€’ 3.70 в€’ в€’ в€’ в€’ в€’ в€’ в€’ в€’ в€’ в€’ 0.1 0.1 0.1 0.55 0.55 2.0 V V ВµA VI = VIH or VIL; 5.5 VO = VCC or GND VI = VCC or GND; IO = 0 5.5 в€’ В±0.25 в€’ 2.0 10 в€’ в€’ В±10.0 ВµA 40 10 ВµA pF 1999 Sep 23 5 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate 74AHC00; 74AHCT00 74AHCT family Over recommended operating conditions; voltage are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage; all outputs HIGH-level output voltage VOL LOW-level output voltage; all outputs LOW-level output voltage II IOZ input leakage current 3-state output OFF current VI = VIH or VIL; IO = в€’50 ВµA VI = VIH or VIL; IO = в€’8.0 mA VI = VIH or VIL; IO = 50 ВµA VI = VIH or VIL; IO = 8 mA VI = VIH or VIL VCC (V) в€’ в€’ 4.5 25 в€’ 0.8 в€’ Tamb (В°C) в€’40 to +85 в€’ 0.8 в€’ в€’40 to +125 UNIT в€’ 0.8 в€’ MIN. TYP. MAX. MIN. MAX. MIN. MAX. 2.0 в€’ 4.4 2.0 в€’ 4.4 V V V 4.5 to 5.5 2.0 4.5 to 5.5 в€’ 4.5 4.4 4.5 4.5 3.94 в€’ в€’ 0 в€’ 0.1 3.8 в€’ в€’ 0.1 3.70 в€’ в€’ 0.1 V V 4.5 5.5 в€’ в€’ в€’ в€’ в€’ в€’ 0.36 0.1 в€’ в€’ 0.44 1.0 В±2.5 в€’ в€’ в€’ 0.55 2.0 V ВµA VI = VIH or VIL; 5.5 VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 VI = VCC or GND; 5.5 IO = 0 VI = VCC в€’ 2.1 V other inputs at VCC or GND; IO = 0 В±0.25 в€’ В±10.0 ВµA ICC ∆ICC quiescent supply current additional quiescent supply current per input pin input capacitance в€’ в€’ в€’ 2.0 1.35 в€’ в€’ 20 1.5 в€’ в€’ 40 1.5 ВµA mA 4.5 to 5.5 в€’ CI в€’ в€’ 3 10 в€’ 10 в€’ 10 pF 1999 Sep 23 6 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate AC CHARACTERISTICS Type 74AHC00 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 3.0 to 3.6 V; note 1 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 15 pF в€’ 50 pF в€’ see Figs 5 and 6 15 pF в€’ 50 pF в€’ 4.5 6.0 7.9 11.4 CL MIN. 25 TYP. MAX. 74AHC00; 74AHCT00 Tamb (В°C) в€’40 to +85 MIN. MAX. в€’40 to +125 MIN. MAX. UNIT 1.0 1.0 9.5 13.0 1.0 1.0 10.0 14.5 ns ns VCC = 4.5 to 5.5 V; note 2 tPHL/tPLH propagation delay nA, nB to nY 3.2 4.5 5.5 7.5 1.0 1.0 6.5 8.5 1.0 1.0 7.0 9.5 ns ns Notes 1. Typical values at VCC = 3.3 V. 2. Typical values at VCC = 5.0 V. Type 74AHCT00 GND = 0 V; tr = tf ≤ 3.0 ns. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS VCC = 4.5 to 5.5 V; note 1 tPHL/tPLH propagation delay nA, nB to nY see Figs 5 and 6 15 pF в€’ 50 pF в€’ 3.3 4.5 6.9 7.9 1.0 1.0 8.0 9.0 1.0 1.0 9.0 10.0 ns ns CL MIN. 25 TYP. Tamb (В°C) в€’40 to +85 MAX. MIN. MAX. в€’40 to +125 MIN. MAX. UNIT Note 1. Typical values at VCC = 5.0 V. 1999 Sep 23 7 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate AC WAVEFORMS 74AHC00; 74AHCT00 handbook, halfpage nA, nB INPUT VM(1) tPHL tPLH nY OUTPUT VM(1) MNA213 FAMILY 74AHC 74AHCT VI INPUT REQUIREMENTS GND to VCC GND to 3.0 V VM(1) INPUT 50% VCC 1.5 V VM(1) OUTPUT 50% VCC 50% VCC Fig.5 The input (nA) to output (nY) propagation delay. handbook, full pagewidth S1 VCC PULSE GENERATOR VI D.U.T. RT CL MNA219 VO 1000 Ω VCC open GND TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND S1 Fig.6 Load circuitry for switching times. 1999 Sep 23 8 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND gate PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm 74AHC00; 74AHCT00 SOT108-1 D E A X c y HE v M A Z 14 8 Q A2 A1 pin 1 index Оё Lp 1 e bp 7 w M L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 Оё inches 0.069 Note 0.010 0.057 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.041 0.228 0.016 8 0o o 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06S JEDEC MS-012AB EIAJ EUROPEAN PROJECTION ISSUE DATE 95-01-23 97-05-22 1999 Sep 23 9 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NAND |
