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Philips Semiconductors 74ALVC02PW - 74ALVC02PW (Philips Semiconductors) - Quad 2-input NOR gate
| Наименование: | 74ALVC02PW |
|---|---|
| Производитель: | Philips Semiconductors |
| Файл: | 74ALVC02PW_Philips Semiconductors.pdf |
| Скачать datasheet: |
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| Описание: | INTEGRATED CIRCUITS DATA SHEET 74ALVC02 Quad 2-input NOR gate Product speciп¬Ѓcation Supersedes data of 2003 Feb 05 2003 Jul 14 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate FEATURES • Wide supply voltage range from 1.65 to 3.6 V • 3.6 V tolerant inputs/outputs • CMOS low power consumption • Direct interface with TTL levels (2.7 to 3.6 V) • Power-down mode • Latch-up performance exceeds 250 mA • Complies with JEDEC standard: JESD8-7 (1.65 to 1.95 V) JESD8-5 (2.3 to 2.7 V) JESD8B/JESD36 (2.7 to 3.6 V). • ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 В°C. SYMBOL tPHL/tPLH PARAMETER propagation delay nA, nB to nY CONDITIONS VCC = 1.8 V; CL = 30 pF; RL = 1 kΩ VCC = 2.5 V; CL = 30 pF; RL = 500 Ω VCC = 2.7 V; CL = 50 pF; RL = 500 Ω VCC = 3.3 V; CL = 50 pF; RL = 500 Ω CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in ВµW). PD = CPD Г— VCC2 Г— fi Г— N + ОЈ(CL Г— VCC2 Г— fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; ОЈ(CL Г— VCC2 Г— fo) = sum of the outputs. 2. The condition is VI = GND to VCC. input capacitance power dissipation capacitance per buffer VCC = 3.3 V; notes 1 and 2 DESCRIPTION 74ALVC02 The 74ALVC02 is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. The 74ALVC02 provides the 2-input NOR function. TYPICAL 2.8 2.0 2.5 2.2 3.5 32 UNIT ns ns ns ns pF pF 2003 Jul 14 2 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate ORDERING INFORMATION PACKAGE TYPE NUMBER 74ALVC02D 74ALVC02PW 74ALVC02BQ FUNCTION TABLE See note 1. INPUT nA L L H H Note 1. H = HIGH voltage level; L = LOW voltage level PINNING Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL 1Y 1A 1B 2Y 2A 2B GND 3A 3B 3Y 4A 4B 4Y VCC DESCRIPTION data output data input data input data output data input data input ground (0 V) data input data input data output data input data input data output supply voltage handbook, halfpage 74ALVC02 TEMPERATURE RANGE в€’40 to +85 В°C в€’40 to +85 В°C в€’40 to +85 В°C PINS 14 14 14 PACKAGE SO14 TSSOP14 DHVQFN14 MATERIAL plastic plastic plastic CODE SOT108-1 SOT402-1 SOT762-1 OUTPUT nB L H L H nY H L L L 1Y 1A 1B 2Y 2A 2B GND 1 2 3 4 5 6 7 MNA214 14 VCC 13 4Y 12 4B 02 11 4A 10 3Y 9 3B 8 3A Fig.1 Pin configuration SO14 and TSSOP14. 2003 Jul 14 3 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate 74ALVC02 handbook, halfpage 1Y 1 VCC 14 13 12 4Y 4B 4A 3Y 3B B MNA215 1A 1B 2Y 2A 2B 2 3 4 5 6 7 Top view GND 8 3A handbook, halfpage A Y GND(1) 11 10 9 MNA951 (1) (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.2 Pin configuration DHVQFN14. Fig.3 Logic diagram (one gate). handbook, halfpage 2 3 ≥1 1 handbook, halfpage 2 3 5 6 8 9 11 12 1A 1B 2A 2B 3A 3B 4A 4B 1Y 1 5 ≥1 4 2Y 4 6 3Y 10 8 9 ≥1 10 4Y 13 11 MNA216 ≥1 13 12 MNA217 Fig.4 Function diagram. Fig.5 IEC logic symbol. 2003 Jul 14 4 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times VCC = 1.65 to 2.7 V VCC = 2.7 to 3.6 V VCC = 1.65 to 3.6 V VCC = 0 V; Power-down mode CONDITIONS 0 0 0 в€’40 0 0 MIN. 1.65 3.6 3.6 VCC 4.6 +85 20 10 74ALVC02 MAX. V V V V UNIT В°C ns/V ns/V LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. When VCC = 0 V (Power-down mode), the output voltage can be 3.6 V in normal operation. 3. For SO14 packages: above 70 В°C derate linearly with 8 mW/K. For TSSOP14 packages: above 60 В°C derate linearly with 5.5 mW/K. For DHVQFN14 packages: above 60 В°C derate linearly with 4.5 mW/K. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = в€’40 to +85 В°C; note 3 VO > VCC or VO < 0 notes 1 and 2 Power-down mode; note 2 VO = 0 to VCC VI < 0 CONDITIONS в€’ в€’0.5 в€’ в€’0.5 в€’0.5 в€’ в€’ в€’65 в€’ MIN. в€’0.5 MAX. +4.6 в€’50 +4.6 В±50 VCC + 0.5 +4.6 В±50 В±100 +150 500 V mA V mA V V mA mA В°C mW UNIT 2003 Jul 14 5 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = в€’40 to +85 В°C VIH HIGH-level input voltage 1.65 to 1.95 0.65 Г— VCC в€’ 2.3 to 2.7 2.7 to 3.6 VIL LOW-level input voltage 2.3 to 2.7 2.7 to 3.6 VOL LOW-level output voltage VI = VIH or VIL IO = 100 ВµA IO = 6 mA IO = 12 mA IO = 18 mA IO = 12 mA IO = 18 mA IO = 24 mA VOH HIGH-level output voltage VI = VIH or VIL IO = в€’100 ВµA IO = в€’6 mA IO = в€’12 mA IO = в€’18 mA IO = в€’12 mA IO = в€’18 mA IO = в€’24 mA ILI Ioff ICC ∆ICC input leakage current VI = 3.6 V or GND 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 3.6 0.0 3.6 3.0 to 3.6 VCC в€’ 0.2 1.25 1.8 1.7 2.2 2.4 2.2 в€’ в€’ в€’ в€’ в€’ 1.51 2.10 2.01 2.53 2.76 2.68 В±0.1 В±0.1 0.2 5 1.65 to 3.6 1.65 2.3 2.3 2.7 3.0 3.0 в€’ в€’ в€’ в€’ в€’ в€’ в€’ в€’ 0.11 0.17 0.25 0.16 0.23 0.30 1.7 2 в€’ в€’ в€’ в€’ в€’ в€’ в€’ VCC (V) MIN. TYP.(1) 74ALVC02 MAX. UNIT в€’ в€’ в€’ 0.7 0.8 0.2 0.3 0.4 0.6 0.4 0.4 0.55 в€’ в€’ в€’ в€’ в€’ в€’ в€’ В±5 В±10 20 750 V V V V V V V V V V V V V V V V V V V ВµA ВµA ВµA ВµA 1.65 to 1.95 в€’ 0.35 Г— VCC V power OFF leakage VI or VO = 3.6 V current quiescent supply current VI = VCC or GND; IO = 0 additional quiescent VI = VCC в€’ 0.6 V; IO = 0 supply current per input pin Note 1. All typical values are measured at Tamb = 25 В°C. 2003 Jul 14 6 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate AC CHARACTERISTICS TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = в€’40 to +85 В°C tPHL/tPLH propagation delay nA, nB to nY see Figs 6 and 7 1.65 to 1.95 2.3 to 2.7 2.7 3.0 to 3.6 Note 1. All typical values are measured at Tamb = 25 В°C. AC WAVEFORMS 1.0 1.0 1.0 1.0 2.8 2.0 2.5 2.2 VCC (V) MIN. TYP.(1) 74ALVC02 MAX. UNIT 4.7 3.1 2.9 2.8 ns ns ns ns handbook, halfpage VI VM GND tPHL VOH tPLH nA, nB input nY output VOL VM tTHL tTLH MNA218 INPUT VCC VM VI VCC VCC 2.7 V 2.7 V tr = tf ≤ 2.0 ns ≤ 2.0 ns ≤ 2.5 ns ≤ 2.5 ns 1.65 to 1.95 V 0.5 Г— VCC 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V 0.5 Г— VCC 1.5 V 1.5 V Fig.6 Inputs nA, nB to output nY propagation delay times. 2003 Jul 14 7 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate 74ALVC02 handbook, full pagewidth VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL MNA616 VCC 1.65 to 1.95 V 2.3 to 2.7 V 2.7 V 3.0 to 3.6 V Definitions for test circuit: RL = Load resistor. VI VCC VCC 2.7 V 2.7 V CL 30 pF 30 pF 50 pF 50 pF RL 1 kΩ 500 Ω 500 Ω 500 Ω VEXT tPLH/tPHL open open open open tPZH/tPHZ GND GND GND GND tPZL/tPLZ 2 Г— VCC 2 Г— VCC 6V 6V CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig.7 Load circuitry for switching times. 2003 Jul 14 8 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate PACKAGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm 74ALVC02 SOT108-1 D E A X c y HE v M A Z 14 8 Q A2 A1 pin 1 index Оё Lp 1 e bp 7 w M L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3 Оё 0.010 0.057 inches 0.069 0.004 0.049 0.019 0.0100 0.35 0.014 0.0075 0.34 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.028 0.004 0.012 8 0o o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 2003 Jul 14 9 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate 74ALVC02 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E A X c y HE v M A Z 14 8 Q A2 pin 1 index A1 Оё Lp L (A 3) A 1 e bp 7 w M detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 Оё 8 0o o 2003 Jul 14 10 Philips Semiconductors Product speciп¬Ѓcation Quad 2-input NOR gate 74ALVC02 DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm D B A A A1 E c terminal 1 index area detail X terminal 1 index area e 2 L e1 b 6 v M C A B w M C y1 C C y 1 Eh 14 7 e 8 13 Dh 0 9 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 |
