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Texas Instruments 74ALVC04 - 74ALVC04 (Texas Instruments) - HEX INVERTER
| Наименование: | 74ALVC04 |
|---|---|
| Производитель: | Texas Instruments |
| Файл: | 74ALVC04_Texas Instruments.pdf |
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| Описание: | SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 D D D D EPIC в„ў (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Package Options Include Plastic Small-Outline (D), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages D, DGV, OR PW PACKAGE (TOP VIEW) 1A 1Y 2A 2Y 3A 3Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 6A 6Y 5A 5Y 4A 4Y description This hex inverter contains six independent inverters designed for 1.65-V to 3.6-V VCC operation. The SN74ALVC04 performs the Boolean function Y = A. The SN74ALVC04 is characterized for operation from –40В°C to 85В°C. FUNCTION TABLE (each inverter) INPUT A H L OUTPUT Y L H logic symbol†1A 2A 3A 4A 5A 6A 1 3 5 9 11 13 1 2 4 6 8 10 12 1Y 2Y 3Y 4Y 5Y 6Y †This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram, each inverter (positive logic) A Y Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright В© 1999, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . В±100 mA Package thermal impedance, ОёJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127В°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182В°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170В°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65В°C to 150В°C †Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) MIN VCC VIH Supply voltage High-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO Low-level input voltage Input voltage Output voltage VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 3 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0 0 1.65 0.65 Г— VCC 1.7 2 0.35 Г— VCC 0.7 0.8 VCC VCC –4 –12 –12 –24 4 12 12 24 5 ns/V mA mA V V V V MAX 3.6 UNIT V IOH High-level High level output current IOL Low-level Low level output current ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature –40 85 В°C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER IOH = –100 ВµA IOH = –4 mA IOH = –6 mA VOH IOH = –12 mA IOH = –24 mA IOL = 100 ВµA IOL = 4 mA IOL = 6 mA IOL = 12 mA IOL = 24 mA VI = VCC or GND VI = VCC or GND, One input at VCC – 0.6 V, IO = 0 Other inputs at VCC or GND TEST CONDITIONS VCC 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3V 1.65 V to 3.6 V 1.65 V 2.3 V 2.3 V 2.7 V 3V 3.6 V 3.6 V 3 V to 3.6 V 3.3 V 3.5 MIN TYP†MAX UNIT VCC–0.2 1.2 2 1.7 2.2 2.4 2 0.2 0.45 0.4 0.7 0.4 0.55 В±5 10 750 ВµA ВµA ВµA pF V V VOL II ICC ∆ICC Ci VI = VCC or GND †All typical values are at VCC = 3.3 V, TA = 25В°C. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V TYP ‡ VCC = 2.5 V В± 0.2 V MIN 1 MAX 3 VCC = 2.7 V MIN MAX 3.3 VCC = 3.3 V В± 0.3 V MIN 1 MAX 2.8 ns UNIT tpd A Y ‡ This information was not available at the time of publication. operating characteristics, TA = 25В°C PARAMETER TEST CONDITIONS f = 10 MHz VCC = 1.8 V TYP ‡ VCC = 2.5 V TYP 23 VCC = 3.3 V TYP 27.5 UNIT pF Cpd Power dissipation capacitance per inverter CL = 0, ‡ This information was not available at the time of publication. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V 2 Г— VCC From Output Under Test CL = 30 pF (see Note A) 1 kΩ S1 Open GND 1 kΩ TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 Г— VCC GND LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at Open (see Note B) Output Waveform 1 S1 at 2 Г— VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V В± 0.2 V 2 Г— VCC From Output Under Test CL = 30 pF (see Note A) 500 Ω S1 Open GND 500 Ω TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 2 Г— VCC GND LOAD CIRCUIT tw Timing Input tsu Data Input VCC/2 VCC VCC/2 0V th VCC VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) tPZL VCC Input VCC/2 tPLH VCC/2 0V tPHL VOH Output VCC/2 VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 VOL Output Waveform 2 S1 at GND (see Note B) Output Waveform 1 S1 at 2 Г— VCC (see Note B) tPZH VCC Input VCC/2 VOLTAGE WAVEFORMS PULSE DURATION VCC/2 0V VCC VCC/2 VCC/2 0V tPLZ VCC VCC/2 VOL + 0.15 V VOL tPHZ VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VCC/2 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74ALVC04 HEX INVERTER SCES117F – JULY 1997 – REVISED FEBRUARY 1999 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V В± 0.3 V 6V From Output Under Test CL = 50 pF (see Note A) 500 Ω S1 Open GND 500 Ω TEST tpd tPLZ/tPZL tPHZ/tPZH S1 Open 6V GND LOAD CIRCUIT tw 2.7 V Timing Input 2.7 V 1.5 V 0V tsu th 2.7 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION Data Input Output Control (low-level enabling) tPZL 2 |
