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Fairchild Semiconductor 74F1071MSA - 74F1071MSA (Fairchild Semiconductor) - 18-Bit Undershoot/Overshoot Clamp
| Наименование: | 74F1071MSA |
|---|---|
| Производитель: | Fairchild Semiconductor |
| Файл: | 74F1071MSA_Fairchild Semiconductor.pdf |
| Скачать datasheet: |
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| Описание: | 74F1071 18-Bit Undershoot/Overshoot Clamp October 1994 Revised August 1999 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground. Features s 18-bit array structure in 20-pin package s FASTВ® Bipolar voltage clamping action s Dual center pin grounds for min inductance s Robust design for ESD protection s Low input capacitance s Optimum voltage clamping for 5V CMOS/TTL applications Ordering Code: Order Number 74F1071SC 74F1071MSA 74F1071MTC Package Number M20B MSA20 MTC20 Package 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Note: Simplified Component Representation FASTВ® is a registered trademark of Fairchild Semiconductor Corporation. В© 1999 Fairchild Semiconductor Corporation DS011685 www.fairchildsemi.com 74F1071 Absolute Maximum Ratings(Note 1) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Input Voltage (Note 2) Input Current (Note 2) ESD (Note 3) Human Body Model (MIL-STD-883D method 3015.7) IEC 801-2 Machine Model (EIAJIC-121-1981) DC Latchup Source Current (JEDEC Method 17) Package Power Dissipation @+70В°C SOIC Package 800 mW В±500 mA В±10 kV В±6 kV В±2 kV в€’65В°C to +150В°C в€’65В°C to +125В°C в€’65В°C to +150В°C в€’0.5V to +6V в€’200 mA to +50 mA Recommended Operating Conditions Free Air Ambient Temperature Reverse Bias Voltage Thermal Resistance (ОёJA in Free Air) SOIC Package SSOP Package 100В°C/W 110В°C/W 0В°C to +70В°C 0V to 5.25 VDC Note 1: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded. Note 3: ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual application. DC Electrical Characteristics Symbol IIH VZ VF ICT CIN Parameter Input HIGH Current Reverse Voltage Forward Voltage Adjacent Input Crosstalk Input Capacitance (small signal @ 1 MHz) 25 13 6.6 в€’0.3 в€’0.5 TA = +25В°C Min Typ 1.5 3 6.9 7.1 в€’0.6 в€’1.1 Max 10 20 7.2 7.5 в€’0.9 в€’1.5 3 в€’0.3 в€’0.5 5.9 TA = 0В°C to +70В°C Min Max 50 100 7.7 8.0 в€’0.9 в€’1.5 Units ВµA V V % pF VBIAS = 0 VDC VBIAS = 5 VDC Conditions VIN = 5.25V; Untested Input @ GND VIN = 5.5V; Untested Input @ GND IZ = 1 mA; Untested Inputs @ GND IZ = 50 mA; Untested Inputs @ GND IF = в€’18 mA; Untested Inputs @ 5V IF = в€’200 mA; Untested Inputs @ 5V www.fairchildsemi.com 2 74F1071 DC Electrical Characteristics Typical Forward and Reverse V/I Characteristics Typical Reverse Conduction Characteristics Typical Forward Conduction Characteristics ESD Network Human Body Model IEC 801-2 CZ 100 pF 150 pF RZ 1500Ω 330Ω Simulated ESD Voltage Clamping Test Circuit 3 www.fairchildsemi.com 74F1071 DC Electrical Characteristics Unclamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) (Continued) Clamped + 1 KV ESD Voltage Waveform (IEC801-2 Network) Unclamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) Clamped - 1 KV ESD Voltage Waveform (IEC801-2 Network) Typical Application 74F1071 ESD Protection of ASIC on User Port www.fairchildsemi.com 4 74F1071 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B 20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number MSA20 5 www.fairchildsemi.com 74F1071 18-Bit Undershoot/Overshoot Clamp Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
