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Fairchild Semiconductor ACE1001 - ACE1001 (Fairchild Semiconductor) - Arithmetic Controller Engine (ACEx) for Low Power Applications
| Наименование: | ACE1001 |
|---|---|
| Производитель: | Fairchild Semiconductor |
| Файл: | ACE1001_Fairchild Semiconductor.pdf |
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| Описание: | CATV/TV/Video Downconverter with Dual Synthesizer FEATURES В• В• В• В• В• В• В• В• В• В• ACD2206 PRELIMINARY DATA SHEET - Rev 1.0 Integrated Downconverter Integrated Dual Synthesizer 256 QAM Compatibility Single +5 V Power Supply Operation Low Noise Figure: 8 dB High Conversion Gain: 31 dB Low Distortion: -53 dBc Three-Wire Interface Small Size -40 В°C to +85 В°C APPLICATIONS В• В• В• В• В• Set Top Boxes CATV Video Tuners Digital TV Tuners CATV Data Tuners Cable Modems S8 Package 28 Pin SSOP PRODUCT DESCRIPTION The ACD2206 uses both GaAs and Si technology to provide the downconverter and dual synthesizer functions in a double conversion tuner gain block, local oscillator, balanced mixer, IF Amplifier, and dual synthesizer. The specifications meet the requirements of CATV/TV/Video and Cable Modem Data applications. The ACD2206 is supplied in a 28 lead SSOP package and requires a single +5 V supply voltage. The IC is well suited for applications where small size, low cost, low auxiliary parts count, and no-compromise performance is important. It provides for cost reduction by lowering the component and packaged IC count and decreasing the amount of labor-intensive production alignment steps, while significantly improving performance and reliability. RFD RF2: 64/65 Prescaler 18 Bit RF2 N Counter RF2 Phase Detector RF2 Charge Pump CPD RFIN+ RFINLow Noise VGA VIF+IFOUTREFIN REFOUT 15 Bit RF2 R Counter VIF+IFOUT+ Mixer Oscillator 15 Bit RF1 R Counter Phase Splitter RFU RF1: 64/65 Prescaler 18 Bit RF1 N Counter RF1 Phase Detector RF1 Charge Pump CPU TCKT OSC OUT Clock Data Enable 22 Bit Data Registar Figure 1: Downconverter Block Diagram 10/2003 Figure 2: Dual Synthesizer Block Diagram ACD2206 1 2 3 4 5 6 7 8 9 10 11 12 13 14 RFIN+ RFINGND ISET TCKT OSCGND OSCGND VSS VSS EN DATA CLK REFIN REFOUT VIF + IFOUT+ VIF + IFOUTGND VSUP OSCOUT GND GND VSS VSS RFD CPD CPU RFU VSYN Figure 3: Pinout 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2 PRELIMINARY DATA SHEET - Rev 1.0 10/2003 ACD2206 Table 1: Pin P IN 1 N AM E RFIN+ D E S C R IP T ION Downconverter Di fferenti al RFInput Downconverter Di fferenti al RFInput Downconverter Ground (Must be connected) Downconverter Gi lbert Cell Current Source Resi stor Osci llator Input Port (Tank ci rcui t connecti on) Osci llator Tank Ci rcui t Ground (Not to be connected to any other ci rcui t ground) Same as Pi n 6 Synthesi zer Ground (Requi red) Synthesi zer Ground (Requi red) 3-Wi re Interface Enable 3-Wi re Interface Data 3-Wi re Interface Clock Crystal Reference Input Crystal Reference Output P IN 28 N AM E VIF+IFOUT+ D E S C R IP T ION Di fferenti al IF Ampli fi er Output, Inducti vely coupled to +VDD Di fferenti al IF Ampli fi er Output, Inducti vely coupled to +VDD Downconverter Ground (Must be connected) Downconverter Supply (+VDD) Osci llator Output (Connected to Synthesi zer RF Input) Downconverter Ground (Must be connected) Downconverter Ground (Must be connected) Synthesi zer Ground (Requi red) Synthesi zer Ground (Requi red) Synthesi zer Downconverter RFInput Synthesi zer Downconverter Charge Pump Output Synthesi zer Upconverter Charge Pump Output Synthesi zer Upconverter RFInput Synthesi zer Supply (+VDD) 2 3 4 RFINGND ISET 27 26 25 VIF+IFOUT GND VSUP 5 TCKT 24 OSCOUT 6 OSCGND 23 GND 7 8 9 10 11 12 13 14 OSCGND V SS V SS EN DATA CLK REFIN REFOUT 22 21 20 19 18 17 16 15 GND V SS V SS RFD CPD CPU RFU VSYN PRELIMINARY DATA SHEET - Rev 1.0 10/2003 3 ACD2206 ELECTRICAL CHARACTERISTICS Table 2: Absolute Minimum and Maximum Ratings PARAMETER Supply Voltage (pins 25, 27 & 28) (pin 15) Voltage on pins 10 through 14, 16 through 19 with VSS = 0 V Input Voltages (pins 1, 2 & 5) Input Power (pins 1 & 2) (pin 5) (pins 13, 16 & 19) Storage Temperature Soldering Temperature Soldering Time Thermal Impedance, ОёJC MIN -0.3 -55 - MAX +9 +6.5 VSYN +0.3 0 +10 +17 +20 +150 260 4 40 UNIT VDC VDC VDC dBm В°C В°C Sec В°C/W Stresses in excess of the absolute ratings may cause permanent damage. Functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability. Table 3: Operating Ranges PAR AME T E R Downconverter Frequenci es RF Input (RF) IF Output (IF) Local Osci llator (LO) (1) MIN 900 35 865 400 400 2 +4.75 -40 T YP 4 +5 - M AX 1200 150 1350 2100 1400 20 10 +5.25 +85 U N IT MHz Synthesi zer Frequenci es Upconverter Synthesi zer (RFU) Downconverter Synthesi zer (RFD) Reference Osci llator (REFIN) Phase Detector Supply Voltage: VDD (pi ns 15, 25, 27, 28) Ambi ent Operati ng Temperature: TA MHz VDC В° C The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications. Notes: (1) Mixer operation is possible beyond these frequencies with slightly reduced performance. 4 PRELIMINARY DATA SHEET - Rev 1.0 10/2003 ACD2206 Table 4: Electrical Specifications - Downconverter Section (TA = 25 Г—C, VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz) PAR AME T E R Conversi on Gai n (1) SSB Noi se Fi gure (1) MIN 28 -10 - T YP 31 8 -59 -90 -5 -10 -70 -50 -10 110 70 900 M AX 10 -53 -85.5 - U N IT dB dB dBc dBc dBm dBc/Hz dBm dBm dBc dBm dBm mA mA mW Cross Modulati on (1), (2), (4) 3rd Order Intermodulati on Di storti on (IMD3) (1), (3), (4) 2-Tone 3rd Order Input Intercept Poi nt (IIP3) (1), (3), (4) LO Phase Noi se (@ 10 KHz Offset) (1) LO Output Power (pi n 24) (1) Spuri ous @ IF Output LO Si gnals and Harmoni cs Beats Wi thi n Output Channel Other Beats from 2 to 200 MHz Other Spuri ous IF Supply Current (pi n 27 & 28) (1), (4) Osc, Phase Spli tter and Mi xer Supply Current (pi n 25) Power Consumpti on Notes: (1) As measured in ANADIGICS test fixture. (2) Two tones: 1085 and 1091 MHz, -40 dBm each, 1091 MHz tone AM-modulated 99% at 15 kHz. (3) Two tones: 1085 and 1091 MHz, -30 dBm each. (4) R1 = 0 Ohms Table 5: Electrical Specifications - Synthesizer Section (TA = +25 Г—C, VDD = +5 VDC) PAR AME T E R Prescalar Input Sensi ti vi ty Upconverter: RFU (pi n 16) (1) Downconverter: RFD (pi n 19) (2) Reference Osci llator Sensi ti vi ty (pi n 13) Charge Pump Output Current (3) SINK SOURCE Supply Current Power Consumpti on Notes: (1) Measured at 250 kHz comparison frequency. (2) Measured at 62.5 kHz comparison frequency. (3) CPU and CPD = Vcc/2. MIN -7 -13 - T YP 0.5 1.25 -1.25 35 165 M AX +20 +20 50 250 U N IT dBm Vp-p C OMME N T S (over operating frequency) mA mA mW PRELIMINARY DATA SHEET - Rev 1.0 10/2003 5 ACD2206 Table 6: Digital Interface Specifications (TA = 25 Г—C, VDD = +5 VDC, ref. Figure 4) P AR AM E T E R Logi c Hi gh Input: VH (pi ns 10, 11, 12) Logi c Low Input: VL (pi ns 10, 11, 12) Logi c Input Current Consumpti on (pi ns 10, 11, 12) Data to Clock Set Up Ti me: tCS Data to Clock Hold Ti me: tCH Clock Pulse Wi dth Hi gh: tCWH Clock Pulse Wi dth Low: tCWL Clock to Load Enable Setup Ti me: tES Load Enable Pulse Wi dth: tEW Ri se Ti me: tR Fall Ti me: tF MIN 2.0 50 10 50 50 50 50 TYP 10 10 M AX 0.8 0.01 U N IT V V mA ns ns ns ns ns ns ns ns DATA CLOCK N20: MSB (R20: MSB) N19 (R19) N10 R10 N9 (R9) (R8) (C2) C2 C1: LSB (C1: LSB) tCWL LE OR LE t CS t CH t CWH t ES t EW Figure 4: Serial Data Input Timing 6 PRELIMINARY DATA SHEET - Rev 1.0 10/2003 ACD2206 PERFORMANCE DATA Figure 5: Typical Upconverter Prescalar Sensitivity vs. Supply Voltage (TA = +25 В°C, fLO1 = 2100 MHz) -7.0 Figure 6: Typical Upconverter Prescalar Sensitivity vs. Local Oscillator Frequency (TA = +25 В°C, VDD = +5 V) -5 Prescalar Sensitivity (dBm) -7.5 Prescalar Sensitivity (dBm) 4.7 4.8 4.9 5.0 5.1 5.2 5.3 -10 -15 -8.0 -20 -25 -8.5 -30 -9.0 -35 500 700 900 1100 1300 1500 1700 1900 2100 Supply Voltage (V) LO1 Frequency (MHz) Figure 7: Typical Downconverter Prescalar Sensitivity vs. Supply Voltage (TA = +25 В°C, fLO2 = 1000 MHz) -16.0 Figure 8: Typical Downconverter Prescalar Sensitivity vs. Local Oscillator Frequency (TA = +25 В°C, VDD = +5 V) -12 Prescalar Sensitivity (dBm) -16.5 Prescalar Sensitivity (dBm) 4.7 4.8 4.9 5.0 5.1 5.2 5.3 -14 -16 -17.0 -18 -20 -17.5 -22 -18.0 Supply Voltage (V) -24 400 600 800 1000 1200 1400 LO2 Frequency (MHz) Figure 9: Typical Local Oscillator Output Power vs. Supply Voltage (TA = +25 В°C, fLO2 = 1042 MHz) -4.5 -5.0 Output Power (dBm) -5.5 -6.0 -6.5 -7.0 4.7 4.8 4.9 5.0 5.1 5.2 5.3 Supply Voltage (V) PRELIMINARY DATA SHEET - Rev 1.0 10/2003 7 ACD2206 LOGIC PROGRAMMING Synthesizer Register Programming The ACD2206 includes two PLL synthesizers. Each synthesizer contains programmable Reference and Main dividers, which allow a wide range of local oscillator frequencies. The 22-bit registers that control the dividers are programmed via a shared three-wire bus, consisting of Data, Clock and Enable lines. The data word for each register is entered serially in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The rising edge of the Clock pulse shifts each data value into the register. The Enable line must be low for the duration of the data entry, then set high to latch the data into the register. (See Figure 4.) Register Select Bits The two least significant bits of each register are register select bits that determine which register is programmed during a particular data entry cycle. Table 7 indicates the register select bit settings used to program each of the available registers. Table 7: Register Select Bits SELEC T B IT S S 2 0 0 1 1 S 1 0 1 0 1 D E S T IN AT ION R E GIS T E R F OR S E R IAL D ATA Reference Divider Register for PLL2 Main Divider Register for PLL2 Reference Divider Register for PLL1 Mai n Di vi der Regi ster for PLL1 Reference Divider Programming The reference divider register for each synthesizer consists of fifteen divider bits, five program mode bits and the two register select bits, as shown |
