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Microchip AN555 - AN555 (Microchip) - Software Implementation of Asynchronous Serial I/O
| Name: | AN555 |
|---|---|
| Producer: | Microchip |
| File: | AN555_Microchip.pdf |
| Download datasheet: |
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| Description: | Software Implementation of Asynchronous Serial I/O AN555 Software Implementation of Asynchronous Serial I/O INTRODUCTION The PIC16CXX microcontrollers from Microchip Technology, Inc., are mid-range, high performance EPROM based 8-bit microcontrollers. Some of the members of this series (like PIC16C71 and PIC16C84) do not have an on-chip hardware asynchronous serial port. This application note describes the Interrupt driven Software implementation of Asynchronous Serial I/O (Half Duplex RS-232 Communications) using PIC16CXX microcontrollers. These microcontrollers can operate at very high speeds with a minimum of 250 ns cycle time (with input clock frequency of 16 MHz). To test the RS232 routines, a simple Digital Volt Meter (DVM)/Analog Data Acquisition Systems has been implemented using PIC16C71 in which upon reception of a command from host (IBM® PC), an 8-bit value of the selected A/D channel is transmitted back to host. Transmission of a byte is performed by calling “PutChar” function and the data byte in the “TxReg” is transmitted out. Before calling this function (“PutChar”), the data must be loaded into TxReg and also made sure that serial port is free. The serial port is free when both _txmtProgress and _rcvOver bits are cleared (see description of these bits in the Serial Status/Control Reg table given later ). 3 Summary of “PutChar” function : 1) Make sure _txmtProgress & _rcvOver bits are cleared 2) Load TxReg with data to be transmitted 3) CALL PutChar function Receive Mode The reception mode implementation is slightly different from the transmit mode. Unlike the transmit Pin (TX pin in the example code is RB7, but could be any I/O pin), the receive pin (RX Pin) must be connected to RTCC/RA4 Pin. This is because in reception, the Start Bit which is asynchronous in nature, must be detected. To detect the start bit, when put in Reception mode, the RTCC module is configured to counter mode . The OPTION register is configured so that RTCC module is put in counter mode (increment on external clock on RTCC/RA4 Pin) and set to increment on falling edge on RTCC/RA4 pin with no prescaler assigned. After this configuration setup, RTCC (File Reg 1) is loaded with 0xFF. A falling edge on RTCC Pin will make RTCC roll over from 0xFF to 0x00, thus generating an interrupt indicating a Start Bit. The RTCC/RA4 pin is sampled again to make sure the transition on RTCC is not a glitch. Once the start bit has been detected, the RTCC module is reconfigured to increment on internal clock and the prescaler is assigned to it depending on input master clock frequency and the baud rate (configured same way as the transmission mode). The software serial port is put in reception mode when a call is made to function “GetChar”. Before calling this function make sure serial port is free (i.e. _txmtProgress and _rcvOver status bits must be 0). On completion of reception of a byte, the data is stored in RxReg and _rcvOver bit is set to 0. IMPLEMENTATION A half duplex Interrupt driven software implementation of RS-232 communications using PIC16C71 is described in detail below. The transmit pin used in the example code is RB7 and receive pin is connected to RTCC/RA4 pin (see Figure 2). Of course these pins are connected with appropriate voltage translation to/from RS-232/ CMOS levels. The voltage translation is given described with schematics in the hardware section of this application note. Transmit Mode The transmit mode in software is quite straight forward to implement using interrupts. Once the input clock frequency and baud rate is known, the number of clock cycles per bit can be computed. The on-chip Real Time Clock Counter (RTCC) along with the prescaler can be used to generate interrupt on RTCC overflow. This RTCC overflow interrupt can be used as timing to send each bit. The Input clock frequency (“_ClkIn”) and the Baud Rate (“_BaudRate”) are programmable by the user and the RTCC time-out value (the period for each bit) is computed at assembly time. Whether the prescaler must be assigned to RTCC or not is also determined at assembly time. This computation is done in the header file “rs232.h”. Note that very high speed transmissions can be obtained if transmission is done with software delays instead of every interrupt driven, however, the processor will be totally dedicated to this job. Summary of “GetChar” function: 1) Make sure _txmtProgress & _rcvOver bits are cleared 2) CALL GetChar function 3) The received Byte is in TxReg after _rcvOver bit is cleared © 1994 Microchip Technology Inc. DS00555B-page 1 3-181 Software Implementation of Asynchronous Serial I/O Parity Generation Parity can be enabled at assembly time by setting “_PARITY_ENABLE” flag to TRUE. If enabled, the parity can be set to either EVEN or ODD parity. In transmission mode, if parity is enabled, the parity bit is computed and transmitted as the ninth bit. On reception, the parity is computed on the received byte and compared to the ninth bit received. If a match does not occur the parity error bit is set in the RS-232 Status/Control Register ( _ParityErr bit of SerialStatus reg). The parity bit is computed using the algorithm shown in Figure 1. This algorithm is highly efficient using PIC16CXX’s SWAPF and XORWF instructions (with ability to have the destination as either file register itself or W register) and the sub-routine (called “GenParity” ) is in file “txmtr.asm”. FIGURE 1 - AN EFFICIENT PARITY GENERATION SCHEME IN SOFTWARE Data Byte Bits Bits XOR 1 XOR Parity Bit XOR 0 Assembly Time Options The firmware is written as a general purpose routines and the user must specify the following parameters before assembling the program. The Status/Control register is also described below: TABLE 1 - LIST OF ASSEMBLY TIME OPTIONS _ClkIn _BaudRate Input clock frequency of the processor. Desired Baud Rate. Any valid value can be used. The highest Baud Rate achievable depends on Input Clock Freq. 600 to 4800 Baud was tested using 4 MHz Input Clock. 600 to 19200 Baud was tested using 10 MHz Input Clock. Higher rates can be obtained using higher Input Clock Frequencies. Once the _BaudRate & _ClkIn are specified, the program automatically selects all the appropriate timings. _DataBits _StopBits _PARITY_ENABLE _ODD_PARITY Can specify 1 to 8 data bits. Limited to 1 Stop Bit. Must be set to 1. Parity Enable Flag. Set it to TRUE or FALSE. If PARITY is used, then set it to TRUE, else FALSE. See “_ODD_PARITY” flag description below. Set it to TRUE or FALSE. If TRUE, then ODD PARITY is used, else mEVEN Parity Scheme is used. This Flag is ignored if _PARITY_ENABLE is set to FALSE. _USE_RTSCTS RTS & CTS Hardware handshaking signals. If set to FALSE, no hardware handshaking is used. If set to TRUE, RTS & CTS use up 2 I/O Pins of PortB. DS00555B-page 2 © 1994 Microchip Technology Inc. 3-182 Software Implementation of Asynchronous Serial I/O TABLE 2 - BIT ASSIGNMENTS OF SERIAL STATUS/CONTROL REGISTER ("SERIALSTATUS" REG) Bit # 0 1 Name _txmtProgress _txmtEnable 1 = Transmission in progress. 0 = Transmission line free. Set this bit to 1 on initialization to enable transmission. This bit may be used to abort a transmission. The transmission is aborted if in the middle of a transmission (i.e. when _txmtProgress bit is 1) _txmtEnable bit is set to 0. This bit gets automatically set when PutChar function is called. 1 = Middle of a byte reception. 0 = Reception of a byte (in RxReg) is complete and is set to 1 when a valid start bit is detected in reception mode. 0 = Completion of reception of a byte. The user’s code can poll this bit after calling “GetChar” function and check to see if it is set. When set, the received byte is in RxReg. Other status bits should also be checked for any reception errors. 1 = Parity error on reception (irrespective of Even Or Odd parity chosen). Not applicable if No Parity is used. 1 = Framing error on reception. Unused _parityBit The 9th bit of transmission or reception. In transmission mode, the parity bit of the byte to be transmitted is set in this bit. In receive mode, the 9th bit (or parity bit) received is stored in this bit. Not Applicable if no parity is used. 2 _rcvProgress 3 _rcvOver 3 4 5 6 7 _ParityErr _FrameErr © 1994 Microchip Technology Inc. DS00555B-page 3 3-183 Software Implementation of Asynchronous Serial I/O Hardware The hardware is primarily concerned with voltage translation from RS-232 to CMOS levels and vice versa. Three circuits are given below and the user may choose which ever best suits his application. The primary difference between each solution is cost versus number of components. Circuits in Figure 3 and 4 are very low cost but have more components than the circuit in Figure 2. The circuit in Figure 2 interfaces to RS-232 line using a single chip (MAX-232) and single +5V supply. The circuit in Figure 3 is a low cost RS-232 Interface but requires two chips and a single +5V supply source. Figure 4 shows a very low cost RS-232 Interface to an IBM PC® with no external power requirements. The circuit draws power from RS-232 line (DTR) and meets the spec of drawing power less than 5mA. This requires that the host to communicate must assert DTR high and RTS low. The power is drawn from DTR line and this requires that DTR to be asserted high and must be at least 7V. The negative -5 to -10 V required by LM339 is drawn from RTS line and thus the host must assert RTS low. This circuit is possible because of the low current consumption of PIC16C71 (typical 2 mA). FIGURE 2 - SINGLE CHIP FOR RS-232 INTERFACE (SINGLE +5V SUPPLY) 0.1µF +5V VDD RTCC RB7 RTS 10µF, 6.3V CTS VCC 16 12 11 9 10 1 2 13 14 8 7 6 RX TX RTS CTS RS-232 Signals 0.1µF 3 VSS 0.1µF PIC16C71 5 15 6 0.1µF MAX-232A FIGURE 3 - LOW COST RS-232 INTERFAC |
