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Hynix Semiconductor HY5R288HCxxx - HY5R288HCxxx (Hynix Semiconductor) - RDRAM
| Name: | HY5R288HCxxx |
|---|---|
| Producer: | Hynix Semiconductor |
| File: | HY5R288HCxxx_Hynix Semiconductor.pdf |
| Download datasheet: |
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| Description: | Direct RDRAM™ 256/288-Mbit (512Kx16/18x32s) Preliminary Overview The Rambus Direct RDRAM™ is a general purpose highperformance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The 256/288-Mbit Direct Rambus DRAMs (RDRAM)are extremely high-speed CMOS DRAMs organized as 16M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology permits 600MHz to 800MHz transfer rates while using conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two bytes (10ns per sixteen bytes). The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The Direct RDRAM's 32 banks support up to four simultaneous transactions. System oriented features for mobile, graphics and large memory systems include power management, byte masking, and x18 organization. The two data bits in the x18 organization are general and can be used for additional storage and bandwidth or for error correction. Figure 1: Direct RDRAM uBGA Package The 256/288-Mbit Direct RDRAMs are offered in a uBGA package suitable for desktop as well as low-profile add-in card and mobile applications. Direct RDRAMs operate from a 2.5 volt supply. Key Timing Parameters / Part Numbers Organizationa 512Kx16x32s 512Kx16x32s 512Kx16x32s 512Kx16x32s 512Kx18x32s 512Kx18x32s 512Kx18x32s 512Kx18x32s I/O Freq. Core Access Time MHz (ns) 600 711 800 800 600 711 800 800 53 45 45 40 53 45 45 40 Part Number HY5R256HC653 HY5R256HC745 HY5R256HC845 HY5R256HC840 HY5R288HC653 HY5R288HC745 HY5R288HC845 HY5R288HC840 Features 0 Highest sustained bandwidth per DRAM device - 1.6GB/s sustained data transfer rate - Separate control and data buses for maximized efficiency - Separate row and column control buses for easy scheduling and highest performance - 32 banks: four transactions can take place simultaneously at full bandwidth data rates Low latency features - Write buffer to reduce read latency - 3 precharge mechanisms for controller flexibility - Interleaved transactions Advanced power management: - Multiple low power states allows flexibility in power consumption versus time to transition to active state - Power-down self-refresh Organization: 2Kbyte pages and 32 banks, x 16/18 - x18 organization allows ECC configurations or increased storage/bandwidth - x16 organization for low cost applications Uses Rambus Signaling Level (RSL) for up to 800MHz operation 0 0 a. The bank “32s” designation indicates that this RDRAM core is composed of 32 banks which use a “split” bank architecture. 0 0 Rev. 0.9 / Dec.2000 This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. 1 Direct RDRAM™ 256/288-Mbit (512Kx16/18x32s) Preliminary Pinouts and Definitions Center-Bonded Devices These tables shows the pin assignments of the center-bonded RDRAM package from the top-side of the package (the view looking down on the package as it is mounted on the circuit board). The mechanical dimensions of this package are shown in a later section. Refer to Section "" on page 60. ( Note : pin#1 is at the A1 position. ) Table 1: Center-Bonded Device (top view) 10 9 VDD GND VDD GND VDD VDD VDD VDD GND VDD GND 8 7 VDD VDD DQA8 CMD DQA7 VDD DQA5 GND DQA3 GNDa DQA1 GNDa CTM VDD CTM VDD ROW 2 GND ROW 0 GND COL3 VDD COL1 VDD DQB1 GND DQB3 GND DQB5 VCMOS DQB7 VDD DQB8 GND VDD 6 5 4 GND GND DQA6 DQA4 DQA2 DQA0 CFM CFM ROW 1 VREF COL4 COL2 COL0 DQB0 DQB2 DQB4 DQB6 GND GND 3 2 1 VDD GND SCK VCMOS GND VDD GND VDDa GND VDD GND GND VDD SIO0 SIO1 GND VDD VDD GND GND VDD GND GND GND GND GND VDD A B C D E F G H J K L M N P R S T U 2 Rev.0.9/Dec.2000 Direct RDRAM™ 256/288-Mbit (512Kx16/18x32s) Preliminary Table 2: Pin Signal SIO1,SIO0 I/O I/O Type CMOSa # Pins center 2 Serial input/output. Pins for reading from and writing to the control registers using a serial access protocol. Also used for power management. Command input. Pins used in conjunction with SIO0 and SIO1 for reading from and writing to the control registers. Also used for power management. Serial clock input. Clock source used for reading from and writing to the control registers Supply voltage for the RDRAM core and interface logic. Supply voltage for the RDRAM analog circuitry. Supply voltage for CMOS input/output pins. Ground reference for RDRAM core and interface. Ground reference for RDRAM analog circuitry. Data byte A. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. DQA8 is not used by RDRAMs with a x16 organization. Clock from master. Interface clock used for receiving RSL signals from the Channel. Positive polarity. Clock from master. Interface clock used for receiving RSL signals from the Channel. Negative polarity Logic threshold reference voltage for RSL signals Clock to master. Interface clock used for transmitting RSL signals to the Channel. Negative polarity. Clock to master. Interface clock used for transmitting RSL signals to the Channel. Positive polarity. Row access control. Three pins containing control and address information for row accesses. Column access control. Five pins containing control and address information for column accesses. Data byte B. Nine pins which carry a byte of read or write data between the Channel and the RDRAM. DQB8 is not used by RDRAMs with a x16 organization. CMD I CMOSa 1 SCK I CMOSa 1 VDD VDDa VCMOS GND GNDa DQA8..DQA0 I/O RSLb 24 1 2 28 2 9 CFM I RSLb RSLb 1 CFMN I 1 VREF CTMN I RSLb RSLb RSLb RSLb RSLb 1 1 CTM I 1 RQ7..RQ5 or ROW2..ROW0 RQ4..RQ0 or COL4..COL0 DQB8.. DQB0 I 3 I 5 I/O 9 Total pin count per package 92 a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero. b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero. Rev.0.9 / Dec.2000 3 Direct RDRAM™ 256/288-Mbit (512Kx16/18x32s) Preliminary DQB8..DQB0 9 RQ7..RQ5 or ROW2..ROW0 3 CTM CTMN SCK,CMD SIO0,SIO1 CFM CFMN 2 2 RCLK RQ4..RQ0 or COL4..COL0 5 DQA8..DQA0 9 RCLK 1:8 Demux TCLK Packet Decode ROWR ROWA 11 5 5 9 ROP DR BR AV Match 1:8 Demux RCLK Control Registers 6 REFR Power Modes COLX 5 5 Packet Decode COLC 5 5 5 7 C 8 COLM 8 R DEVID XOP DX BX COP DC BC M S Match XOP Decode Match MB MA Mux Row Decode DM Write Buffer Mux Mux PRER ACT Sense Amp 64x72 SAmp SAmp SAmp PREX Column Decode & Mask DRAM Core 64x72 512x128x144 Bank 0 64x72 0 72 SAmp SAmp SAmp PREC RD, WR Internal DQB Data Path 0 72 Internal DQA Data Path 0/1 0/1 72 Bank 1 1/2 1/2 Bank 2 72 RCLK 9 9 ••• 9 ••• 9 RCLK SAmp SAmp SAmp 14/15 13/14 Bank 13 Bank 14 Bank 15 ••• 13/14 14/15 15 SAmp SAmp SAmp Write Buffer 1:8 Demux Write Buffer 1:8 Demux 9 9 SAmp SAmp SAmp 15 SAmp SAmp SAmp 17/18 16/17 16 16 Bank 16 Bank 17 Bank 18 ••• 16/17 17/18 TCLK 9 9 TCLK ••• 8:1 Mux ••• 8:1 Mux 9 9 SAmp SAmp SAmp 30/31 29/30 Bank 29 Bank 30 Bank 31 SAmp SAmp SAmp 29/30 30/31 31 Figure 2: 256/288 Mbit Direct RDRAM Block Diagram 4 31 Rev.0.9/Dec.2000 Direct RDRAM™ 256/288-Mbit (512Kx16/18x32s) Preliminary General Figure 2: is a block diagram of the 256/288 Mbit Direct RDRAM. It consists of two major blocks: a “core” block built from banks and sense amps similar to those found in other types of DRAM, and a Direct Rambus interface block which permits an external controller to access this core at up to 1.6GB/s. amps of the RDRAM. These pins are de-multiplexed into a 24-bit ROWA (row-activate) or ROWR (row-operation) packet. COL Pins: The principle use of these five pins is to manage the transfer of data between the DQA/DQB pins and the sense amps of the RDRAM. These pins are de-multiplexed into a 23-bit COLC (column-operation) packet and either a 17-bit COLM (mask) packet or a 17-bit COLX (extended-operation) packet. Control Registers: The CMD, SCK, SIO0, and SIO1 in the upper center of Figure 2:. They are used to pins appear write and read a block of control registers. These registers supply the RDRAM configuration information to a controller and they select the operating modes of the device. The REFR value is used for tracking the last refreshed row. Most importantly, the five bit DEVID specifies the device address of the RDRAM on the Channel. ACT Command: An ACT (activate) command from an ROWA packet causes one of the 512 rows of the selected bank to be loaded to its associated sense amps (two 512 bytes sense amps for DQA and two for DQB). PRER Command: A PRER (precharge) command from an ROWR packet causes the selected bank to release its two associated sense amps, permitting a different row in that bank to be activated, or permitting adjacent banks to be activated. Clocking: The CTM and CTMN pins (Clock-To-Master) generate TCLK (Transmit Clock), the internal clock used to transmit read data. The CFM and CFMN pins (Clock-FromMaster) generate RCLK (Receive Clock), the internal clock signal used to receive write data and to receive the ROW and COL pins. RD Command: The RD (read) command causes one of the 64 dualocts of one of the sense amps to be transmitted on the DQA/DQB pins of the Channel. DQA,DQB Pins: These 18 pins carry read (Q) and write (D) data across the Channel. They are multiplexed/de-multiplexed from/to two 72-bit data paths (running at one-eighth the d |
