Datasheets search
Datasheets search archive of electronic components datasheets
For search electronic components datasheets (documentation) use the search form or sortcuts for quick datasheet search. Our base has over 1 000 000 downloadable pdf datasheets. If you don't find necessary datasheet, please send feedback to project administrator. We hope, what our electronic components datasheets and documentation archive help you find necessary documentation.
More 1 000 000 datasheets example: LM317
Hynix Semiconductor HY5RS573225F - HY5RS573225F (Hynix Semiconductor) - 256 GDDR3 SDRAM
| Name: | HY5RS573225F |
|---|---|
| Producer: | Hynix Semiconductor |
| File: | HY5RS573225F_Hynix Semiconductor.pdf |
| Download datasheet: |
|
| Description: | HY5RS573225F 256M (8Mx32) GDDR3 SDRAM HY5RS573225F This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.4 / Apr. 2004 1 HY5RS573225F Revision History Revision No. 0.1 0.2 0.3 0.4 History Defined target spec. Full Revision Defined IDD Spec. Insert AC parameter (-12/ -13/ -14/ -15) Draft Date Apr. 2003 Oct. 2003 Dec. 2003 Apr. 2004 Remark Rev. 0.4 / Apr. 2004 2 HY5RS573225F DESCRIPTION The Hynix HY5RS573225 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. The Hynix HY5RS573225 is internally configured as a quad-bank DRAM. The Hynix HY5RS573225 uses a double data rate architecture to achieve high-speed opreration. The double date rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the Hynix HY5RS573225 consists of a 4n-bit wide, every two-clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the Hynix HY5RS573225 is burst oriented; accesses start at a selected locations and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ of WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the Hynix HY5RS573225 must be initialized. FEATURES • • • • • • • • • VDD=1.8V ± 0.1V, VDDQ=1.8V ± 0.1V Single ended READ Strobe (RDQS) per byte Single ended WRITE Strobe (WDQS) per byte Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle Calibrated output drive Differential clock inputs (CK and CK#) Commands entered on each positive CK edge RDQS edge-aligned with data for READs; with WDQS center-aligned with data for WRITEs Four internal banks for concurrent operation • • • • • • • • • • Data mask (DM) for masking WRITE data 4n prefetch Programmable burst lengths: 4 32ms, 4K-cycle auto refresh Auto precharge option Auto Refresh and Self Refresh Modes 1.8v Pseudo Open Drain I/O Concurrent Auto Precharge support tRAS lockout support, Active Termination support Programmable Write latency(1,2 or 3) ORDERING INFORMATION Part No. HY5RS573225F-12 HY5RS573225F-13 HY5RS573225F-14 HY5RS573225F-15 HY5RS573225F-16 HY5RS573225F-18 HY5RS573225F-20 HY5RS573225F-22 VDD=1.8V, VDDQ=1.8V Power Supply Clock Frequency 800MHz 750MHz 700MHz 650MHz 600MHz 550MHz 500MHz 450MHz Max Data Rate 1600Mbps/pin 1500Mbps/pin 1400Mbps/pin 1300Mbps/pin 1200Mbps/pin 1100Mbps/pin 1000Mbps/pin 900Mbps/pin POD_18 12mmx12mm 144Ball FBGA Interface Package Rev. 0.4 / Apr. 2004 3 HY5RS573225F BALLOUT CONFIGURATION 2 3 4 5 6 7 8 9 10 11 12 13 B WDQS0 RDQS0 VSSQ DQ3 DQ2 DQ0 DQ31 DQ29 DQ28 VSSQ RDQS3 WDQS3 C DQ4 DM0 VDDQ VDDQ DQ1 VDDQ VDDQ DQ30 VDDQ VDDQ DM3 DQ27 D DQ6 DQ5 VSSQ VSSQ VSSQ VDD VDD VSSQ VSSQ VSSQ DQ26 DQ25 E DQ7 RFU3 VDD VSS VSSQ VSS VSS VSSQ VSS VDD RFU4 DQ24 F DQ17 DQ16 VDDQ VSSQ VSS therm VSS therm VSS therm VSS therm VSSQ VDDQ DQ15 DQ14 G DQ19 DQ18 VDDQ VSSQ VSS therm VSS therm VSS therm VSS therm VSSQ VDDQ DQ13 DQ12 H WDQS2 RDQS2 VDDQ VSSQ VSS therm VSS therm VSS therm VSS therm VSSQ VDDQ RDQS1 WDQS1 J DQ20 DM2 VDDQ VSSQ VSS therm VSS therm VSS therm VSS therm VSSQ VDDQ DM1 DQ11 K DQ21 DQ22 VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ9 DQ10 L DQ23 A3 VDD VSS RFU2 VDD VDD RFU1 VSS VDD A4 DQ8 M VREF A2 A10 RAS RESET CKE RFU5 ZQ CS A9 A5 VREF N A0 A1 A11 BA0 CAS CK CK WE BA1 A8/AP A6 A7 8M x 32 Configuration Refresh Count Bank Address Row Address Column Address AP Flag 2M x 32 x 4 banks 4k BA0, BA1 A0~A11 A0~A7, A9 A8 Package Top View (see the balls through the package) Rev. 0.4 / Apr. 2004 4 HY5RS573225F FUNCTIONAL BLOCK DIAGRAM 4Banks x 2Mbit x 32 I/O Double Data Rate Synchronous DRAM CKE CK CK# #s# RAS# CAS# WE# BANK3 BANK2 BANK1 12 ROW ADDRESS MUX 12 12 BANK0 ROW ADDRESS LATCH & DECODER CONTROL LOGIC COMMAND DECODE BANK3 BANK2 BANK1 128 READ LATCH CCL0, CCL1 32 32 32 32 MUX 32 DATA CK/ CK# DLL MODE REGISTERS 14 REFRESH COUNTER 40% BANK0 MEMORY ARRAY (4096x512x128) DRVRS RDQS(0~3) SENSE AMPLIFIERS RDQS GENERATOR 4 RDQS(0~3) DQ(0~31) 66,536 2 INPUT REGISTERS I/O GATING DM MASK LOGIC BANK CONTROL LOGIC 128 4 4 16 512 (x128) 4 4 4 4 4 22 22 22 22 22 RCVRS WDQS(0~3) A0~A11 BA0, BA1 14 ADDRESS REGISTER 2 128 COLUMN DECODER CLK 9 COLUMN ADDRESS COUNTER LATCH 7 2 WRITE FIFO & DRIVERS MASK 4 4 22 DM(0~3) CK OUT CK IN 22 128 DATA 22 22 COL0, COL1 4 Rev. 0.4 / Apr. 2004 5 HY5RS573225F BALLOUT DESCRIPTIONS FBGA BALLOUT N7, N8 SYMBOL CK, CK# TYPE Input DESCRIPTION Clock: CK and Ck# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations(all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK#, CKE and RES are disabled during POWER-DOWN. Input buffers (excluding CKE and RES) are disabled during SELF REFRESH. Chip Select: CS# enables (registered LOW)and disables (registered HIGH) the command decoder. All commands (except DATA TERMINATOR DISABLE) are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS# and WE#(along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on rising and falling edges of WDQS. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit(A8) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0, BA1) or all banks (A8 HIGH). The address inputs also provide the opcode during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Data Input/Output: Data Input/Output: Data Input/Output: Data Input/Output: READ Data Strobe: Output with read data. RDQS is edgealigned with read data. It is used to capture data. WRITE Data strobe: Input with write data. WDQS is center aligned to the input data. 6 M7 CKE Input M10 CS# Input M5, N6, N9 RAS#, CAS#, WE# DM0-DM3 Input C3, J12, J3, C12 Input N5, N10 BA0, BA1 Input N2:3, M3, L3, L12, M12, N12:13, N11, M11, M4, N4 A0-A11 Input B7, C6, B6, B5, C2, D3, D2, E2 L13, K12:13, J13, G13:12, F13:12 F3:2, G3:2, J2, K2:3, L2 E13, D13:12, C13, B10:9, C9, B8 B3, H12, H3, B12 B2, H13, H2, B13 Rev. 0.4 / Apr. 2004 DQ0-7 DQ8-15 DQ16-23 DQ24-31 RDQS0-3 WDQS0-3 I/O I/O I/O I/O Output Input HY5RS573225F BALLOUT DESCRIPTIONS FBGA Ball Out C4:5 C7:8, C10:11 F4, F11, G4, G11, H4, H11 J4, J11, K4, K11 B4, B11, D4:6, D9:11, E6, E9, F5, F10, G5, G10, H5, H10, J5, J10, K5, K10 D7:8, E4, E11, L4, L11 E5, E7:8, E10, K6:9, L5, L10 M2, M13 M9 M6 F6:9, G6:9, H6:9, J6:9 E3, E12, L6, L9, M8 SYMBOL VDDQ TYPE Supply DESCRIPTION DQ Power Supply: +1.8V ± 0.100V. Isolated on the die for improved noise immunity. DQ Ground: Isolated on the die for improved noise immunity. Power Supply: +1.8V ± 0.100V Ground Reference voltage. External reference pin for Auto-calibration. Reset pin. The RES pin is a VDDQ CMOS input. NC or Could be used as VSS for thermal purpose Reserved for Future Use -CONTINUE VSSQ VDD VSS VREF ZQ RES VSStherm RFU Supply Supply Supply Supply REFERENCE Input NC, Supply NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins deemed to be of importance. Rev. 0.4 / Apr. 2004 7 HY5RS573225F Initialization and Power Up GDDR3 SGRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must be first applied to VDD and VDDQ simul-taneously, and then to VREF. VREF can be applied any time after VDDQ. Once power has been applied and the clocks are stable the GDDR3 device requires 200us before the RES pin transitions to high. Upon power-up and after the clock is stable, the on die termination value for the address and control pins will be set, based on the state of CKE when the RES pin transitions from LOW to HIGH. On the rising edge of RES, the CKE pin is latched to determine the on die termination value for the address and control lines. If CKE is sampled at a logic LOW then the on die termination will |
