Electronics News

Archive : 3 June 2015 year

Synthesis solution said to address SoC design productivity gap


Looking to address the productivity challenges faced by RTL designers, Cadence has launched Genus Synthesis Solution. According to the company, Genus incorporates a multilevel massively parallel architecture that can deliver an improvement in synthesis throughput of up to five times. In addition, the tool can halve the number of iterations between unit and chip level synthesis.

Paul Cunningham, vp of R&D, noted: "The productivity gap is widening and there has been a call to action to develop evaluation tools which boost productivity dramatically. If we're serious about closing this gap, we have to target a number of things."

Genus features a massively parallel architecture, enabling physically aware context generation, unified global routing and power, performance and area optimisation at a global analytical architecture level.

Cunningham said that, while physical aspects of chip design have been parallelised, the core part of the design flow involving timing optimisation hasn't been distributed. "We have done this by going in at the flow level so that any subset of a design can be cut out and sent to another machine. The data structure remains the same as the original and you can keep 'chopping' the design up."

He noted that, while certain parts of a design are critical and can't be cut across, this process needs to be done in a way that minimises the amount of data traffic. However, the result is said to be full timing and physical context for any element of the design.

The first level of distribution is at 100k instances or more, with timing driven across multiple machines and CPUs. The second level address blocks of around 10k instances, again across multiple machines and CPUs. Finally, there is algorithm level multithreading on one machine.

Cunningham said a 34million instance design – equivalent to more than 100m gates – took two days to run using 16 quad core CPUs.

Genus can also share the same data engine as the recently announced Innovus place and route package, with a common interface improving ease of use and designer productivity.

Graham Pitcher

Source:  www.newelectronics.co.uk

Small and discreet data glasses for everyday use


In a move intended to counter the lukewarm reception by consumers of products such as Google Glass, researchers at the Fraunhofer Institute for Applied Optics and Precision Engineering IOF, have developed a design which they say is small and unobtrusive. They also claim the glasses can correct farsightedness.

Data glasses usually consist of a micro-display that generates the image and optics that project the image onto the desired object or position. While the micro-display of Fraunhofer's design measures 8 x 15mm, similar in size to conventional models, the optics are only 5mm long. "We designed our glasses to be small and discreet," says Dr Peter Schreiber, group manager in the Micro-optical Systems department at Fraunhofer. "This allows us to obtain the same results with a much shorter structure."

The design uses a nanoscale lattice structure applied to a glass plate as a light guide. This helps to position information on the lens exactly where the viewer is looking, rather than projecting information on the edge of the lens.

People who need prescription glasses usually have difficulty reading the information displayed in data glasses. Fraunhofer claims users of its glasses can enter their vision data into an app on their smartphone, which sends the relevant information via Bluetooth. The device then adjusts images in such a way that they appear sharp. Frauhofer says the glasses may also be able to partly compensate for other vision problems, such as astigmatism and shortsightedness.

As well as tourism, the data glasses could offer solutions in applications including health monitoring and industrial applications.

Tom Austin-Morgan

Source:  www.newelectronics.co.uk

Micron launches 16Gbyte TLC NAND on 16nm process


Micron Technology has expanded its flash storage portfolio with the addition of what it calls a 'purpose built solution for cost sensitive consumer applications seeking high performance and reliability'.

The triple level cell (TLC) NAND device, built on Micron's 16nm process, is said to deliver features which suit applications like USB drives and consumer solid state drives.

"Our new TLC NAND technology meets rising demand for reliable high capacity storage," said Kevin Kilbuck, director of NAND planning. "We see 16nm TLC as an excellent solution for 2015 consumer applications as we drive toward 3D NAND TLC production in 2016."

Graham Pitcher

Source:  www.newelectronics.co.uk

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