Two years after announcing Stratix 10 SoC FPGAs, Altera has disclosed more details about how the devices – being built on Intel's 14nm TriGate process – achieve the claimed performance.
Alongside quad Cortex-A53 processors, the parts also take advantage of Intel's Embedded Multi Interconnect Bridge (EMIB) and what's called the Hyperflex architecture.
Chris Balough, senior director of SoC product marketing, noted: "Stratix 10 is the flagship. This is the most significant step forward in high end FPGAs. The level of integration is amplified by Intel's process and packaging technology."
The move to Hyperflex was said by Balough to not have been made lightly. "We have been working on the architecture for about five years to make sure we're confident." He added the greatest benefits will be found in datapath applications. "They tend to be the ones you want to speed the most," he added.
Stratix 10 FPGAs will be able to attain GHz frequencies, according to Balough. "If you want GHz frequencies, you have two choices: either wider buses to move more things in parallel or you have to address routing delays."
In his view, wider buses is an inadequate solution, because it affects power consumption and die size. "So we have addressed the problem by adding registers."
HyperFlex sees registers distributed across all core interconnect routing segments. This is said to allow such design techniques such as register retiming and pipelining to be applied – techniques claimed as not practical in conventional FPGAs.
"HyperFlex is not just for extra throughput," Balough pointed out, "it's also for those who want smaller FPGAs that use less power."
In an example application, Altera pointed to a data centre application that previously required five Stratix V FPGAs and which consumed 120W. The application is said to run on one Stratix 10 SoC FPGA which consumes 44W.
Similarly, in a wireline optical switch application, one 900k LE Stratix V device drawing 47W can be replaced with a 650k LE Stratix 10 drawing 28W.
Meanwhile, EMIB technology enables 3D heterogeneous integration. While the FPGA die will be made on Intel's 14nm process, the 'tiles' which provide additional functionality will be made on a 20nm line. Altera will initially provide PCIe Gen 3 tiles running at up to 30Gbit/s, but plans a range of other comms tiles, including optical interfaces.
Balough said 'eight to 10' Stratix 10 parts will be available, with the largest device featuring 5.5million logic elements. First shipments of Stratix 10 devices are planned for Q4 2015.