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FPGA logic architecture extended



Flex Logix has extended its core FPGA logic architecture to include block RAM (BRAM) and DSP cores. According to the company, adding low latency memory and signal processing capabilities broadens the range of applications its EFLX embedded FPGA in SoC architecture can address.

EFLX technology allows SoC designers to embed FPGAs into their designs, enabling key functions to be optimised or customised after the device is made. It also allows for in system upgrading.

By adding BRAM and DSP, Flex Logix expands the tool kit available to designers for this post-production flexibility. For instance, applications such as encryption, networking and signal processing require blocks of RAM to be integrated into the FPGA to provide fast local memory to implement buffers, scratchpads, FIFOs, and other low-latency memory that improves performance.

Flex Logix says its architecture can now support any amount of single or dual port RAM in any width. Along with ECC, parity or no error checking, the approach is said to offer more flexibility than is found in standalone FPGAs.

Meanwhile, Flex Logix has added an EFLX Logic core with 40 MACs with 22bit inputs and 48bit accumulation. The MACs can be combined for double precision and pipelined for high throughput. They can also be used as complex number MACs for certain DSP algorithms.

EFLX technology is targeted at TSMC’s 28HPM/C processes, with a version for being developed for TSMC’s 40LP/ULP processes. According to the company, it expects to develop a version for TSMC’s 16nm FinFET process.

Author
Graham Pitcher

Source:  www.newelectronics.co.uk

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