TSMC plans to use EUV at 5nm, but may use it earlier
TSMC hasn't given up hope on using EUV lithography at the 10nm node, but it appears to be more likely to be introduced at the 5nm node. Speaking on a conference call, Mark Liu, TSMC's president and co-CEO, pictured, said: "We are planning to exercise EUV at 7nm and are currently planning to use EUV at 5nm. But it depends on certain development criteria and milestones."
He added that TSMC's assessment of the technology shows that EUV will reduce the number of masking layers needed at 5nm and provide better control.
Despite recently selling its shareholding in ASML, TSMC continues to work closely with the tools developer. "We have made very good progress on source power," Liu continued, "as well as on photoresists. However, the current challenge is more on the masks and we are working with ASML."
Source: www.newelectronics.co.ukPrevious news All news of day Next news
Other news ...
- 3D printed 'smart cap' can sense spoiled food
- UltraSOC adds Tensilica support
- Government to fund testing of automated vehicles
- Anelastic nanowires could enable stretchable electronic devices
- Self-powered switch range and evaluation kit simplifies design of wireless controls
- MCU extends battery life of embedded devices in IoT applications
- - March
- - June