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National Semiconductor 54ABT16500W-QML - 54ABT16500W-QML (National Semiconductor) - 18-Bit Universal Bus Transceivers with TRI-STATE Outputs
| Наименование: | 54ABT16500W-QML |
|---|---|
| Производитель: | National Semiconductor |
| Файл: | 54ABT16500W-QML_National Semiconductor.pdf |
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| Описание: | 54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs 54ABT16500 July 1998 54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE В® Outputs General These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active-high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active high and OEBA is active low). To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Features n Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode n Flow-through architecture optimizes PCB layout n Guaranteed latch-up protection n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9687001 Ordering Code Military 54ABT16500W-QML Package Number WA56A 56-Lead Cerpack Package TRI-STATE В® is a registered trademark of National Semiconductor Corporation. В© 1998 National Semiconductor Corporation DS100225 www.national.com 1 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 1 Connection Diagram Pin Assignment for Cerpack DS100225-1 Function Table (Note 1) Inputs OEAB L H H H H H H LEAB X H H L L L L CLKAB X X X ↓ ↓ A X L H L H X X Output B Z L H L H B0 (Note 2) B0 (Note 3) H L Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low. www.national.com 2 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 2 Logic Diagram DS100225-2 3 www.national.com PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 3 Absolute Maximum Ratings (Note 4) Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic VCC Pin Potential to Ground Pin Input Voltage (Note 4) Input Current (Note 4) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current в€’65ЛљC to +150ЛљC в€’55ЛљC to +125ЛљC в€’55ЛљC to +175ЛљC в€’0.5V to +7.0V в€’0.5V to +7.0V в€’30 mA to +5.0 mA Over Voltage Latchup (I/O) 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input в€’55ЛљC to +125ЛљC +4.5V to +5.5V (∆V/∆t) 50 mV/ns 20 mV/ns в€’0.5V to 5.5V в€’0.5V to VCC twice the rated IOL (mA) в€’500 mA Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Output Short-Circuit Current Output High Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current Additional ICC/Input Dynamic ICC (Note 6) No Load 0.23 в€’100 в€’275 50 100 1.0 68 1.0 2.5 mA ВµA ВµA mA ВµA mA mA mA/ MHz Max Max 0.0 Max Max Max Max Max VOUT = 0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH An or Bn Outputs Low OEn = VCC, All Others at VCC or GND VI = VCC в€’ 2.1V All Others at VCC or GND Outputs Open Transparent Mode One Bit Toggling, 50% Duty Cycle Note 6: Guaranteed, but not tested. Parameter Min Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current Output Leakage Current 4.75 54ABT 54ABT 54ABT 2.5 2.0 2.0 ABT16500 Typ Max Units V 0.8 в€’1.2 V V V V 0.55 5 5 7 в€’5 в€’5 V 50 в€’50 ВµA ВµA ВµA ВµA V ВµA VCC Conditions Recognized HIGH Signal Recognized LOW Signal Min Min Min Min Max Max Max 0.0 0 в€’ 5.5V 0 в€’ 5.5V IIN = в€’18 mA IOH = в€’3 mA IOH = в€’24 mA IOL = 48 mA VIN = 2.7V (Note 6) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 6) VIN = 0.0V IID = 1.9 ВµA All Other Pins Grounded VOUT = 2.7V; OE, OE = 2.0V VOUT = 0.5V; OE, OE = 2.0V www.national.com 4 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 4 DC Electrical Characteristics Symbol Parameter Min Max Units VCC Conditions CL = 50 pF; RL = 500Ω TA = 25ЛљC (Note 7) TA = 25ЛљC (Note 7) VOLP VOLV Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL 1.1 -1.7 V V 5.0 5.0 Note 7: Max number of outputs defined as (n). n в€’ 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter 54ABT TA = в€’55ЛљC to +125ЛљC VCC = 4.5V–5.5V CL = 50 pF Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay A or B to B or A Propagation Delay LEAB or LEBA to B or A Propagation Delay CLKAB or CLKBA to B or A Propagation Delay OEAB or OEBA to B or A Propagation Delay OEAB or OEBA to B or A 150 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 6.5 7.0 7.0 7.8 7.5 8.0 6.3 6.5 7.2 6.8 ns ns ns ns Max MHz ns Units Fig. No. Figure 4 Figure 4 Figure 4 Figure 6 Figure 6 AC Operating Requirements Symbol Parameter 54ABT TA = в€’55ЛљC to +125ЛљC VCC = 4.5V–5.5V CL = 50 pF Min ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) ts(H) ts(L) th(H) th(L) tw(H) tw(L) Setup Time, A to CLKAB Hold Time, A to CLKAB Setup Time, B to CLKBA Hold Time, B to CLKBA Setup Time, A to LEAB or B to LEBA, CLK High Hold Time, A to LEAB or B to LEBA, CLK High Setup Time, A to LEAB or B to LEBA, CLK Low Hold Time, A to LEAB or B to LEBA, CLK Low Pulse Width, LEAB or LEBA, High 4.5 4.5 0 0 4.0 4.0 0 0 1.5 1.5 1.5 1.5 4.5 4.5 1.5 1.5 3.3 3.3 ns ns ns ns ns ns ns ns Max ns Units Fig. No. Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 7 Figure 5 5 www.national.com PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 5 AC Operating Requirements Symbol Parameter (Continued) 54ABT TA = в€’55ЛљC to +125ЛљC VCC = 4.5V–5.5V CL = 50 pF Min Max ns Units Fig. No. tw(H) tw(L) Pulse Width, CLKAB or CLKBA, High or Low 3.3 3.3 Figure 5 Capacitance Symbol CIN CI/O (Note 8) Parameter Input Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF Conditions, TA = 25ЛљC VCC = 0.0V VCC = 5.0V Note 8: CI/O is measured at frequency f = 1 MHz per MIL-STD-883B, Method 3012. www.national.com 6 PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1 cmserv Proof 6 AC Loading DS100225-3 DS100225-4 *Includes jig and probe capacitance. FIGURE 1. Standard AC Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100225-6 DS100225-5 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times FIGURE 2. VM = 1.5V Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns tf 2.5 ns FIGURE 3. Test Input Signal Requirements DS100225-8 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100225-7 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 7 www.national.com PrintDate=1998/07/14 PrintTime=11:08:56 43605 ds100225 Rev. No. 1 cmserv Proof 7 54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted Book Extract End 56-Lead Cerpack NS Package Number WA56A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 FranГ§ais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 www.national.com 8 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the r |
