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National Semiconductor 54ACT112 - 54ACT112 (National Semiconductor) - Dual JK Negative Edge-Triggered Flip-Flop
| Наименование: | 54ACT112 |
|---|---|
| Производитель: | National Semiconductor |
| Файл: | 54ACT112_National Semiconductor.pdf |
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| Описание: | 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop September 1998 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General The ’ACT112 contains two independent, high-speed JK flip-flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features n ’ACT112 has TTL-compatible inputs n Outputs source/sink 24 mA n Standard Microcircuit Drawing (SMD) 5962-8995001 Connection Diagram Pin Assigment for DIP and Flatpack Pin s Pin Names J1, J2, K1, K2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q2, Q1, Q2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) Direct Set Inputs (Active LOW) Outputs DS100976-3 Pin Assigment for LCC DS100976-5 FACTв„ў is a trademark of Fairchild Semiconductor Corporation. В© 1998 National Semiconductor Corporation DS100976 www.national.com Logic Symbols DS100976-2 DS100976-1 IEEE/IEC DS100976-4 Truth Table Inputs SD L H L H H H H CD H L L H H H H CP X X X M M M M J X X X h l h l K X X X h h l l Outputs Q H L H Q0 L H Q0 Q L H H Q0 H L Q0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial M = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. www.national.com 2 Logic Diagram (One Half Shown) DS100976-6 3 www.national.com Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = в€’0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = в€’0.5V VO = VCC + O.5 DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) в€’0.5V to +7.0V в€’20 mA +20 mA в€’0.5V to VCC + 0.5V в€’20 mA +20 mA в€’0.5V to VCC +0.5V Junction Temperature (TJ) CDIP 175ЛљC Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (∆V/∆t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC в€’55ЛљC to +125ЛљC 125 mV/ns В± 50 mA В± 50 mA в€’65ЛљC to +150ЛљC Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACTв„ў circuits outside databook specifications. DC Characteristics for ’ACT Family Devices Symbol VIH VIL VOH Parameter Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(Note 3) Maximum Quiescent Supply Current TA = в€’55ЛљC to +125ЛљC Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 VIN = VIL or VIH 3.70 4.70 0.1 0.1 VIN = VIL or VIH 0.5 0.5 V IOL = 24 MA IOL = 24 mA (Note 2) 5.5 5.5 5.5 5.5 5.5 VI = VCC, GND VI = VCC в€’ 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V V IOH = в€’24 mA IOH = в€’24 mA (Note 2) IOUT = 50 ВµA V V V VOUT = 0.1V or VCC в€’ 0.1V VOUT = 0.1V or VCC в€’ 0.1V IOUT = в€’50 ВµA Units Conditions В± 1.0 1.6 50 в€’50 80.0 ВµA mA mA mA ВµA Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. www.national.com 4 AC Electrical Characteristics for ’ACT Family Devices Symbol Parameter VCC (V) (Note 4) fmax tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay CPn to Qn or Qn Propagation Delay CPn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Propagation Delay CDn or SDn to Qn or Qn Note 4: Voltage Range 5.0 is 5.0V В± 0.5V TA = в€’55ЛљC to +125ЛљC CL = 50 pF Min 80 1.0 1.0 1.0 1.0 14.0 14.0 13.5 13.5 Max Units 5.0 5.0 5.0 5.0 5.0 MHz ns ns ns ns AC Operating Requirements: Symbol Parameter VCC (V) (Note 5) tS Setup Time, HIGH or LOW Jn or Kn to CPn tH Hold Time, HIGH or LOW Jn or Kn to CPn tW trec Pulse Width CPn or CDn or SDn Recovery Time CDn or SDn to CPn Note 5: Voltage Range 5.0 is 5.0V В± 0.5V TA = в€’55ЛљC to +125ЛљC CL = 50 pF Guaranteed Minimum 8.0 Units 5.0 ns 5.0 1.5 ns 5.0 5.0 5.0 3.0 ns ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Max 10.0 60 Units pF pF Conditions VCC = OPEN VCC = 5.0V 5 www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Ceramic Dual-in-line Package Number J16A 16-Lead Cerpack Package Number W16A www.national.com 6 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Leadless Chip Carrier Package Number E20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: support@nsc.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 FranГ§ais Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: sea.support@nsc.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 www.national.com National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. |
