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STMicroelectronics 74AC00B - 74AC00B (STMicroelectronics) - QUAD 2-INPUT NAND GATE
| : | 74AC00B |
|---|---|
| : | STMicroelectronics |
| : | 74AC00B_STMicroelectronics.pdf |
| datasheet: |
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| : | SN54AC00, SN74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS524C – AUGUST 1995 – REVISED SEPTEMBER 1996 D D EPIC ™ (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), DIP (N) Packages, Ceramic Chip Carriers (FK), Flat (W), and DIP (J) Packages SN54AC00 . . . J OR W PACKAGE SN74AC00 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) description The ‘AC00 contain four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A S B or Y = A + B in positive logic. The SN54AC00 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74AC00 is characterized for operation from – 40°C to 85°C. FUNCTION TABLE (each gate) INPUTS A H L X B H X L OUTPUT Y L H H 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC 4B 4A 4Y 3B 3A 3Y SN54AC00 . . . FK PACKAGE (TOP VIEW) 1Y NC 2A NC 2B 4 5 6 7 8 3 2 1 20 19 18 17 16 15 14 9 10 11 12 13 1B 1A NC VCC 4B 4A NC 4Y NC 3B NC – No internal connection A logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 2 4 5 9 10 12 13 11 4Y 8 3Y 6 2Y logic diagram (positive logic) & 3 1Y Y B † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1996, Texas Instruments Incorporated POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2Y GND NC 3Y 3A 1 SN54AC00, SN74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS524C – AUGUST 1995 – REVISED SEPTEMBER 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): D package . . . . . . . . . . . . . . . . . . . 1.25 W DB package . . . . . . . . . . . . . . . . . . 0.5 W N package . . . . . . . . . . . . . . . . . . . . 1.1 W PW package . . . . . . . . . . . . . . . . . . 0.5 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils, except for the N package, which has a trace length of zero. recommended operating conditions (see Note 3) SN54AC00 MIN VCC VIH Supply voltage High-level input voltage VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V VIL VI VO IOH Low-level input voltage Input voltage Output voltage High-level output current VCC = 3 V VCC = 4.5 V VCC = 5.5 V VCC = 3 V IOL ∆t /∆v Low-level output current Input transition rise or fall rate VCC = 4.5 V VCC = 5.5 V 0 – 55 VCC = 4.5 V VCC = 5.5 V 0 0 2 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –12 –24 –24 12 24 24 8 125 0 – 40 0 0 MAX 6 SN74AC00 MIN 2 2.1 3.15 3.85 0.9 1.35 1.65 VCC VCC –12 –24 –24 12 24 24 8 85 ns / V °C mA mA V V V V MAX 6 UNIT V TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54AC00, SN74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS524C – AUGUST 1995 – REVISED SEPTEMBER 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 3V IOH = – 50 µA IOH = – 12 mA IOH = – 24 mA IOH = – 50 mA† IOH = – 75 mA† IOH = 50 µA IOL =12 mA IOL = 24 mA IOL = 50 mA† IOL = 75 mA† II ICC Ci VI = VCC or GND VI = VCC or GND, IO = 0 4.5 V 5.5 V VOH 3V 4.5 V 5.5 V 5.5 V 5.5 V 3V 4.5 V 5.5 V VOL 3V 4.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V ± 0.1 2 ±1 40 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 0.1 0.1 0.1 0.5 0.5 0.5 1.65 1.65 ±1 20 µA µA pF MIN 2.9 4.4 5.4 2.56 3.86 4.86 TA = 25°C TYP MAX SN54AC00 MIN 2.9 4.4 5.4 2.4 3.7 4.7 3.85 3.85 0.1 0.1 0.1 0.44 0.44 0.44 V MAX SN74AC00 MIN 2.9 4.4 5.4 2.46 3.76 4.76 V MAX UNIT VI = VCC or GND 5V 2.6 † Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) A or B TO (OUTPUT) Y MIN 2 1.5 TA = 25°C TYP MAX 7 5.5 9.5 8 SN54AC00 MIN 1 1 MAX 11 9 SN74AC00 MIN 2 1 MAX 10 8.5 UNIT ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) A or B TO (OUTPUT) Y MIN 1.5 1.5 TA = 25°C TYP MAX 6 4.5 8 6.5 SN54AC00 MIN 1 1 MAX 8.5 7 SN74AC00 MIN 1.5 1 MAX 8.5 7 UNIT ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd Power dissipation capacitance TEST CONDITIONS CL = 50 pF, f = 1 MHz TYP 40 UNIT pF POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54AC00, SN74AC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCAS524C – AUGUST 1995 – REVISED SEPTEMBER 1996 PARAMETER MEASUREMENT INFORMATION TEST tPLH/tPHL S1 Open Input (see Note B) tPLH In-Phase Output tPHL Out-of-Phase Output LOAD CIRCUIT 50% VCC 50% VCC VCC 50% VCC 50% VCC 0V tPHL VOH 50% VCC VOL tPLH VOH 50% VCC VOL 2 × VCC From Output Under Test CL = 50 pF (see Note A) 500 Ω S1 Open 500 Ω VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright © 1998, Texas Instruments Incorporated |
