The archive is a schematic circuit of LCD TVs Panasonic TX-32LX60F / P, TX-26LX60F / P chassis GLP21
1) Wiring analog multiplexer. Distribution of inputs and outputs on the connector pins JK3001 and JK3002.
2) Detail Concept A base unit with a video processor IC1501.
3) Detail Concept A base unit with a control processor.
4) Voltage 5V Voltage 8V Voltage Selector 12-16 volts generator voltage of 33 V.
5) Voltage 3.3V standby. Node supply voltage of 3.3 V. The distribution of the input and output signals to the input pins A12 (AV3). The distribution of power terminal pin A7.
6) The distribution of inputs and outputs on the connector pins JK3000 (AV1). Distribution of inputs and outputs on the connector pins JK3050 (AV2).
7) Cascades feed AV1 and AV2 video connectors with SCART. Schematic diagram of the board tuner B.
8) Connect the connector pins A2 to the LCD-Pane. Wiring diagram tuner card to the base chassis. The protection scheme. Cascades photodetector signals and display. Circuit protection circuit STBY 3,3 V. The shifter level. Circuit of the chip audiomatrix.
9) Wiring chip memory EEPROM. Connecting the DAC and operational amplifier mode HDMI. Circuit of the inverter power backlight.
10) Scheme keyboard control KEY CONTROL. Telephone amplifier audio signals.
11) The circuit board receiver and display control scheme V. board external connectors AV3.
12) The circuit board power supply R.