SK hynix Unveils Low-Power LPDDR6 SDRAM Breakthrough at ISSCC 2026

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SK hynix Unveils Low-Power LPDDR6 SDRAM Breakthrough at ISSCC 2026

SK hynix showcased its cutting-edge 16 Gb LPDDR6 SDRAM at the International Solid-State Circuits Conference (ISSCC) 2026. The new memory implements the JEDEC LPDDR6 standard, delivering up to 14.4 Gb/s per pin at 1.025 V while reducing power consumption by 20% and boosting bandwidth by 50% compared to previous generations.

LPDDR6 SDRAM chip micrograph from SK hynix presentation

Key Specifications and Performance Gains

Capacity: 16 Gb
Process node: 1c-nm (6th-generation 10nm-class)
Speed: Up to 14.4 Gb/s per pin (pin bandwidth 10,667 Mbps)
Voltage: 1.025 V (VDD2C), 0.875 V (VDD2D) - lower than LPDDR5's 1.1 V
Power savings: Overall 20% reduction; up to 45% lower IDD2N current at low frequencies

Compared to LPDDR5/LPDDR5X, LPDDR6 offers higher clock speeds (up to 2,677 MHz), a fixed 2:1 clock-to-write ratio, and enhanced efficiency for demanding applications.

LPDDR6 topology and architecture diagram — LPDDR6 dual-subchannel topology

Five Key Innovations

SK hynix highlighted five architectural advancements:

Efficiency Mode with dual-subchannel architecture: Enables parallel operation or powers down inactive sub-channels to save energy.
LDO-based WCK tree: Reduces write clock jitter by 30% for better timing and stability.
Dynamic write NT-ODT: Dynamically adjusts on-die termination for improved signal integrity and lower power.
Fast CS control: Optimizes chip-select handling across frequency ranges, cutting setup/hold delays and current draw.
System meta mode: Interleaves metadata into data packets, eliminating dedicated pins and reducing complexity/power.

WCK distribution network with LDO regulator — WCK distribution network and global LDO regulator diagram

Dynamic write NT-ODT timing and test data — Dynamic write NT-ODT with test results

Target Applications

The new LPDDR6 targets high-performance mobile devices (smartphones, tablets), edge AI computing, automotive intelligence, and AI data centers, where power efficiency and high bandwidth are critical.

By validating LPDDR6 in silicon, SK hynix confirms the standard's real-world potential, paving the way for mass production and broader adoption in on-device AI products.

Metadata interleaving within data packets — Metadata integration within data packets illustration