Low-Power SRAM with 64 Mbit and 32 Mbit

Renesas announced the development of the R1WV6416R Series of 64 Mbit Advanced Low-Power SRAM (Advanced LPSRAM) and the R1LV3216R Series of 32 Mbit Advanced LPSRAM products with compact chip size. Sample shipments of the 32 Mbit products will begin in April 2008, and of the 64 Mbit products in July, in Japan. These two They will be available in different packages and specifications, such as access time, for a total of twelve 64 Mbit products and eight 32 Mbit products to meet a wide range of requirements in fields including industry, office equipment, consumer electronics, automotive systems, and communications equipment. To accommodate a variety of applications, these two series are being offered in several different packages: TSOP I (48-pin), μTSOP (52-pin), and for 64 Mbit products FBGA (48-ball).

 The TSOP I and μTSOP packages have the same dimensions as those of previous 16 Mbit products, and the ball layout of the FBGA package is signal pin compatible. Advanced LPSRAM uses a stacked capacitor memory cell configuration, an approach with a proven track record in DRAM cells. It virtually eliminates soft errors caused by alpha radiation or high-energy neutron radiation, which can be a problem with ultrafine SRAM. In addition, this memory cell configuration avoids the unintended formation of an parasitic thyristor, which can generate spurious current flows and cause latchups. Advanced LPSRAM products currently in mass production include 4 Mbit and 16 Mbit products, as well as 32 Mbit products comprising two 16 Mbit chips stacked in a single package. The two new series respond to demand for increased capacity with compact single-chip 32 Mbit products and 64 Mbit products comprising two 32 Mbit chips stacked in a single package.

 The R1WV6416R Series of 64 Mbit Advanced LPSRAM products and the R1LV3216R Series of 32 Mbit Advanced LPSRAM products are available with access times of 55 ns (nanoseconds) or 70 ns, and in TSOP I (48-pin), μTSOP (52-pin), or (for 64 Mbit products) FBGA (48-ball) packages. The package of the TSOP I (48-pin) products is identical to that of current 16 Mbit products, and the package of the μTSOP (52-pin) is identical to that of current 8 Mbit, 16 Mbit, and 32 Mbit products. FBGA (48-ball) products have a ball layout that is backward compatible with that of current 4 Mbit, 8 Mbit, 16 Mbit, and 32 Mbit products. Advanced LPSRAM eliminates soft errors through the use of stacked capacitors and reduces the surface area of each memory cell by employing a vertical configuration in which the stacked capacitors are formed in a layer above the transistors.

 The SRAM cells use polysilicon TFTs*5 as P-channel load transistors. By forming these in a layer above the other transistors and reducing the number of transistors underneath, the memory cell surface area is reduced. This is why the 32 Mbit R1LV3216R Series has the smallest chip size in the industry for a 32 Mbit low-power SRAM product. Furthermore, Advanced LPSRAM requires no refreshes and therefore uses less power than pseudo SRAM (PSRAM), which uses SDRAM or DRAM memory cells as the SRAM interface. This makes it suitable for low-power applications that use batteries for data backup.