Lattice Semiconductor announced the ispLEVER 7.1 FPGA design tool suite. The release delivers a number of new functional and performance-enhancing features, including the dedicated FPGA Simultaneous Switching Output (SSO) Analyzer. The SSO Analyzer enables FPGA designers to actively analyze and optimize I/O pin placement and output switching characteristics to minimize undesirable noise and ground bounce on a printed circuit board. An enhanced Power Calculator enables FPGA designers to analyze and optimize power requirements early in their design. This release marks the addition of Synplicity’s Synplify Pro and Aldec’s Active-HDL Lattice Edition as principal elements of the ispLEVER FPGA design flow.
Mentor Graphics Precision RTL synthesis and ModelSim simulator continue to be supported as standalone tools for Lattice FPGA design and are available directly from Mentor Graphics. Both Lattice and Mentor Graphics remain fully committed to support Lattice’s existing and future programmable devices with Mentor Graphics tools. Lattice’s ispLEVER 7.1 for Windows, Linux and UNIX users is available immediately without charge for customers with active design tool maintenance. The full ispLEVER design tool suite starts at a price of $895 for the Windows version.
