Archive : 21 March 2016 year
Faradion wins Government funding for sodium-ion development23:15
Three weeks after announcing a partnership aimed at developing sodium ion cells for solar applications, Sheffield based Faradion will share £1.3million of Government funding from a competition aimed at cutting vehicle emissions. Joining Faradion in the latest project are Scottish company AGM Batteries and WMG, from the University of Warwick.
At the beginning of March 2016, Faradion, Moixa Technology and WMG announced plans to develop sodium-ion cells as a low cost alternative to lithium-ion batteries for solar energy storage, with the work part funded by Innovate UK.
Announced in the recent budget, the Government is making £38.2m available to fund innovative ways to reduce vehicle emissions. The funding combines £30m from the Office for Low Emission Vehicles (OLEV) and £8.2m from Innovate UK. According to the Government, projects will begin to unveil working prototypes by 2018 and the results could feature in passenger cars from 2020.
Roland Meister, head of transport at Innovate UK said: “This £38m of Government support means that more than 130 innovative organisations now have the chance to get their ideas off the drawing board and, potentially, into the cars and trucks of the future.”
In the earlier announcement, Faradion said it will bring its knowledge of sodium-ion battery technology to the partnership, will provide photovoltaic design, build and test expertise. WMG, meanwhile, will provide large scale prototype manufacturing and electrode coating capabilities.
Francis Massin, CEO of Faradion, said: “This partnership with Moixa and WMG offers a great opportunity, not just for Faradion, but also for global CO2 reduction.”
Pic: A 48 cell battery pack design by Williams Advanced Engineering, featuring Faradion’s 3Ahr Na-ion cells.
Silicon photonics lane rates pushed to 50Gbit/s23:12
Using process and design optimisations, Belgian nanoelectronics research centre imec has upgraded its integrated silicon photonics platform with technology that is said to support non return to zero (NRZ) lane rates of 50Gbit/s. The development, according to imec, is an important milestone in the realisation of high data rate silicon integrated optical interconnects.
Alongside improving the operating speed of silicon based travelling wave Mach-Zehnder modulators and ring modulators, imec says it has also developed a C-band GeSi electro-absorption modulator with an electro-optical bandwidth in excess of 50GHz. This, it explains, will enable NRZ modulation at data rates of 56Gbit/s and beyond.
The 50Gbit/s components are included in imec’s 200mm silicon photonics multiproject wafer portfolio and are supported by a Process Design Kit.
Pic: Bare silicon photonics dies from imec’s iSiPP25G+ process extracted from 200mm wafers.
EU project to develop multicore programming approach23:09
A three year European programme with funding of €3.9million, is bringing together industry and researchers to develop a tool chain for what the partners call ‘efficient, standardised and real time capable programming’.
The ARGO project, being coordinated by Karlsruhe Institute of Technology (KIT), is working on a method to convert model based applications into multicore optimised C code with guaranteed real-time constraints.
Today, says the project, programmers have to adapt their code to the target hardware architecture, which brings high cost and prevents the code from being transferred to other architectures.
“Two of the most important requirements of future applications are increased performance in real time and further reduction of costs without adversely affecting functional safety,” said project coordinator Professor Jürgen Becker from KIT. “For this, multicore processors have to make available the required performance spectrum at minimum energy consumption in an automated and efficiently programmed manner.”
Programming of heterogeneous multicore processors is complex and these programs have to be tailored precisely to the target hardware.
“Under ARGO, a new standardisable tool chain for programmers is being developed,” said Prof Becker. “Even without precise knowledge of the complex parallel processor hardware, programmers can control the process of automatic parallelisation in accordance with the requirements. This results in a significant improvement of performance and a reduction of costs.”
In the future, says the team, the ARGO tool chain could be used to manage parallelisation complexity and adaptation to the target hardware in a largely automated manner and at relatively low cost.
Other partners in ARGO are: University of Rennes (France); Technological Educational Institute of Western Greece; German Aerospace Centre; Fraunhofer Institute for Integrated Circuits IIS; Recore Systems; Scilab Enterprises; and AbsInt Angewandte Informatik.
Pic: The ARGO team will use DLR’s AVES flight simulator to test its developments
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