QuickLogic announces the addition of a SPI (serial peripheral interconnect) Host Controller to its customer specific standard product (CSSP) functional library. The SPI interface gives mobile device designers a low pin-count alternative to SDIO or mini-PCI for implementing high speed connections to wireless modules and other peripheral functions. QuickLogic's CSSP approach blends fixed logic blocks with an array of low-power customisable building blocks (CBBs) for implementing additional standards-based or custom functions. This approach offers development teams a customisable platform that addresses the need to meet cost, battery life and PCB-space requirements, while also maintaining the flexibility to evolve designs as market demands change in the future. QuickLogic's CSSP platforms include the PolarPro and ArcticLink platform families, offering a range of options in size and capacity.
When implemented in QuickLogic's programmable platform products, an SDIO Host Controller requires 15 customisable building blocks (CBBs), and PCI requires 6 to 9 CBBs depending on the configuration. The SPI Host Controller requires three CBBs and four I/Os, freeing resources on the CSSP platform for the implementation of additional functions (devices with from 8 to 240 CBBs are available in QuickLogic's range). The SPI interface is capable of operating at clock rates to 52 MHz. It comes with a low-overhead SPI software driver that can be customised for specific peripherals for higher performance.
