Development environment allows FPGAs to be used ‘as if they weren’t there’
In a move which it says will bring better power performance to data centres, Xilinx has launched SDAccel. The package, part of Xilinx' SDx family, combines an architecturally optimising compiler, supporting OpenCL, C and C++, libraries, development boards, and a 'CPU/GPU like' development environment.
Giles Peckham, European marketing manager for Xilinx, said there are two issues facing data centres. "PCI Express based apps need to run at less than 25W, but are performance limited. Apps that need higher performance are power limited, so developers tend to use GPUs because they are more powerful. However, both approaches have reached a performance per Watt limit." He added that developers of such applications don't have to understand hardware or FPGA place and route. "We're offering a design environment that allows FPGAs to be used as if they weren't there."
According to Xilinx, SDAccel's compiler delivers up to 25 times better performance/Watt compared to CPUs or GPUs. It allows software developers to use new or existing OpenCL, C and C++ code to create high performance accelerators, optimised for memory, dataflow and loop pipelining in a range of data centre applications.
Xilinx says developers can use a familiar workflow to optimise their applications and to take advantage of FPGA platforms without having to know about FPGAs. The integrated design environment executes the application on data centre ready FPGA platforms, with automatic instrumentation insertion for all supported development targets.
SDAccel will be available initially for x86 based processors, but Peckham said that ARM based devices will be addressed in 2015.
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